Interlaced layout configuration for differential pairs of interc

Details Interlaced layout configuration for differential pairs of interc Interlaced layout configuration for differential pairs of interc

1995-09-14

1996-12-03

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257773, 257758, 257664, 365207, 365 63, H01L 2710, H01L 2348, G11C 506, G11C 1300

Patent

active

055811264

ABSTRACT:
An SRAM array configuration includes even bitline pairs which each laterally interchange at a crossover placed at the 1/2 point along the length of the bitline pairs, and which SRAM array includes odd bitline pairs which each laterally interchange at each of two associated crossovers at the 1/4 and 3/4 points along the length of the bitline pairs. Consequently, signals or noise resident on neighboring bitline pairs or other neighboring conductive structure couple a common-mode voltage onto a given bitline pair through lateral parasitic capacitance to the neighboring conductive structure. Such a common-mode noise signal does not affect the differential signal on the given bitline pair. This interlaced configuration is useful for one or more pairs of differential signal lines, whether used within an SRAM array or for global interconnect between circuit blocks.

REFERENCES:
patent: 5014110 (1991-05-01), Satoh
patent: 5025299 (1991-06-01), Arnould
patent: 5140556 (1992-08-01), Cho et al.
patent: 5272665 (1993-12-01), Uesugi
patent: 5280443 (1994-01-01), Hidaka et al.

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