Interlaced delay-locked loops for controlling memory-circuit...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

Reexamination Certificate

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C327S261000

Reexamination Certificate

active

07042265

ABSTRACT:
For control, some memory circuits use a delay-locked loop to generate a set of signals, each delayed a different amount relative a reference signal. However, as circuits get faster and faster, conventional delay-locked loops require use of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal. In addition, the first and second loops are synchronized.

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