Static information storage and retrieval – Addressing – Sync/clocking
Patent
1977-12-30
1978-09-26
Fears, Terrell W.
Static information storage and retrieval
Addressing
Sync/clocking
365183, 307238, G11C 1140
Patent
active
041175468
ABSTRACT:
Disclosed is an interlaced serial-parallel-serial (SPS) charge coupled device (CCD) memory with improved clocking. By performing the interlacing as well as the serial-parallel-serial function with only seven clock pulses, less metallurgy and consequently less space per bit on a semiconductor chip is required. By reducing the number of clock requirements, the supporting logic circuitry is simplified permitting a larger portion of the semiconductor chip area to be used for data bit storage.
REFERENCES:
patent: 3763480 (1973-08-01), Weimer
Anantha Narasipur Gundappa
Cases Moises
Chang Fung Yuel
Rubin Barry Jay
Fears Terrell W.
Galanthay Theodore E.
International Business Machines - Corporation
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