Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1995-06-05
1998-09-29
Everhart, Caridad
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257774, 257750, H01L 2700
Patent
active
058148892
ABSTRACT:
A die 810 has an outer, annular via 814 filled with conductive material in order to electrically shield an inner via 816. A die 820 can be electrically shielded from another area 822 by use of a wall 823 having a trench with oxidized side walls and a conductive filling.
REFERENCES:
patent: 3256465 (1966-06-01), Weissenstern et al.
patent: 3343256 (1967-09-01), Smith et al.
patent: 3372070 (1968-03-01), Zuk
patent: 3418545 (1968-12-01), Hutson
patent: 3445686 (1969-05-01), Rutz
patent: 3454835 (1969-07-01), Rosvold
patent: 3456335 (1969-07-01), Hennings et al.
patent: 3462650 (1969-08-01), Hennings et al.
patent: 3648131 (1972-03-01), Stuby
patent: 3796927 (1974-03-01), Boyle et al.
patent: 3798513 (1974-03-01), Ono
patent: 3885196 (1975-05-01), Fischer
patent: 3959579 (1976-05-01), Johnson
patent: 3962052 (1976-06-01), Abbas et al.
patent: 3969745 (1976-07-01), Blocker, III
patent: 3982268 (1976-09-01), Anthony et al.
patent: 4074342 (1978-02-01), Honn et al.
patent: 4097890 (1978-06-01), Morris et al.
patent: 4104674 (1978-08-01), Lorenze, Jr. et al.
patent: 4188709 (1980-02-01), Lorenze, Jr. et al.
patent: 4263341 (1981-04-01), Martyniak
patent: 4275410 (1981-06-01), Grinberg et al.
patent: 4368503 (1983-01-01), Kurosawa et al.
patent: 4379307 (1983-04-01), Soclof
patent: 4467343 (1984-08-01), Herberg
patent: 4528072 (1985-07-01), Kurosawa et al.
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4613891 (1986-09-01), Ng et al.
patent: 4670764 (1987-06-01), Benjamin et al.
patent: 4701424 (1987-10-01), Mikkor
patent: 4720738 (1988-01-01), Simmons
patent: 4761681 (1988-08-01), Reid
patent: 4839309 (1989-06-01), Easter et al.
patent: 4839510 (1989-06-01), Okabe et al.
patent: 4862322 (1989-08-01), Bickford et al.
patent: 4897708 (1990-01-01), Clements
patent: 4935800 (1990-06-01), Taguchi
patent: 4954875 (1990-09-01), Clements
patent: 4982266 (1991-01-01), Chatterjee
patent: 5057895 (1991-10-01), Beasom
patent: 5196920 (1993-03-01), Kumamoto et al.
patent: 5198695 (1993-03-01), Hanes et al.
patent: 5268326 (1993-12-01), Lesk et al.
patent: 5317183 (1994-05-01), Hoffman et al.
patent: 5363550 (1994-11-01), Aitken et al.
patent: 5421083 (1995-06-01), Suppelsa et al.
patent: 5475255 (1995-12-01), Joardar et al.
Stanley Wolf, Silicon Processing for the VLSI Era vol. 2 (1992) Lattice Press California, pp. 546-547.
Everhart Caridad
Harris Corporation
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