Intergratable load voltage sampling circuit for R.M.S. load aver

Details Intergratable load voltage sampling circuit for R.M.S. load aver Intergratable load voltage sampling circuit for R.M.S. load aver

1984-05-07

1986-03-25

Leung, Philip H.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

323281, 323237, G05F 156

Patent

active

045786321

ABSTRACT:
An integratable load voltage sampling circuit utilizes a plurality of current-mirrors. One of the current mirrors is switched into conduction during a load-current conduction time interval, while another current mirror operates during the entire source half-cycle during which the first current mirror is pulsed to conduct. The total current from the plurality of current mirrors is summed and compared to a reference level; the difference in magnitude between the sampled and reference values is integrated, with respect to time, to provide a load conduction-angle adjustment signal having a magnitude varying as the root-mean-square magnitude of the average load voltage.

REFERENCES:
patent: 4063149 (1977-12-01), Crowle
patent: 4435678 (1984-03-01), Joseph et al.
patent: 4477737 (1984-10-01), Ulmer et al.
patent: 4498041 (1985-02-01), Kuwahara
patent: 4513178 (1985-04-01), Hing et al.
patent: 4528494 (1985-07-01), Bloomer

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