Interference grasping test mode circuit for a semiconductor memo

Details Interference grasping test mode circuit for a semiconductor memo Interference grasping test mode circuit for a semiconductor memo

1992-12-23

1995-05-23

Nguyen, Hoa T.

Excavating

371 221, 365201, G11C 2900

Patent

active

054187907

ABSTRACT:
A test mode circuit for a memory device for, in a test mode, transforming information to be stored in the memory device and information being read from the memory device and selecting simultaneously information stored in cell arrays in the memory device, so as to grasp interferences between adjacent cells and between adjacent data bus lines. The circuit comprises a cell array section having a plurality of cell arrays for storing input data therein, a first switching section for selecting one of test and normal modes and selecting one of the plurality of cell arrays in the normal mode, a first logic section for transferring desired information simultaneously to the cell array section in response to a clock signal in the test mode, a second logic section responsive to the clock signal for outputting directly output data signals from the plurality of cell arrays or inverting the data signals and outputting the inverted data signals, a third logic section for, in the test mode, inputting output signals from the second logic section and discriminating whether the data signals from the plurality of cell arrays are the same, and a second switching section for selecting, as its output signal, an output, signal from the third logic section in the test mode and the data signal from the selected one of cell arrays in the normal mode.

REFERENCES:
patent: 5016220 (1991-05-01), Yamagata
patent: 5148398 (1992-09-01), Kohno
patent: 5157629 (1992-10-01), Sato et al.

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