Interference free D-type flip-flop

Details Interference free D-type flip-flop Interference free D-type flip-flop

1985-09-26

1987-11-10

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307481, 3072722, 377117, 377105, H03K 326, H03K 3284, H03K 2116, H03K 19094

Patent

active

047059656

ABSTRACT:
An electronic D-type flipflop includes two storage elements and two transmission gates wherein each gate includes only one MOS transistor. In the first gate the MOS transistor is of a first conductivity type and it is of a second conductivity type in the second gate. The MOS transistors each receive the same clock signal at their gate electrode. Because it is not necessary to form an inverted clock signal, problems due to phase differences between the clock signal and its inverse are precluded. Each of the storage cells includes a pair of inverters which are coupled end-around. The transmission characteristic of the forward inverting circuit is adapted in such a way that it compensates for the voltage drop across the preceding transmission gate. Only a small substrate surface area will be required when the flipflop is used in an integrated circuit.

REFERENCES:
patent: 3588848 (1971-06-01), Van Beek
patent: 3812384 (1974-05-01), Skorup
patent: 4250406 (1981-02-01), Alaspa
patent: 4302690 (1981-11-01), Gollinger et al.
patent: 4390987 (1983-06-01), Best
patent: 4484087 (1984-11-01), Mazin et al.

Affiliated with

Also associated with

Rating

Interference free D-type flip-flop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interference free D-type flip-flop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interference free D-type flip-flop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1069751