Interfacing hardware emulation to distributed simulation...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C703S014000, C703S016000, C703S020000, C703S023000

Reexamination Certificate

active

07424416

ABSTRACT:
A system for interfacing hardware emulation to software simulation environments may include a simulation node configured to simulate a first portion of a system under test and a hardware emulation node configured to emulate a second portion of the system under test. The hardware emulation node may also be configured to exchange simulation information (such as representations of signal values obtained as output from the emulated portion of the system under test) with the simulation node. The hardware emulation node may contain a field programmable gate array devices (FPGA) configured to perform the hardware emulation. The FPGA may be mounted on an expansion board, such as a PCI (Peripheral Component Interconnect) board.

REFERENCES:
patent: 4456994 (1984-06-01), Segarra
patent: 4821173 (1989-04-01), Young et al.
patent: 4937173 (1990-06-01), Kanda et al.
patent: 5185865 (1993-02-01), Pugh
patent: 5327361 (1994-07-01), Long et al.
patent: 5339435 (1994-08-01), Lukin et al.
patent: 5398317 (1995-03-01), Nugent
patent: 5442772 (1995-08-01), Childs et al.
patent: 5455928 (1995-10-01), Herlitz
patent: 5519848 (1996-05-01), Wloka et al.
patent: 5625580 (1997-04-01), Read et al.
patent: 5634010 (1997-05-01), Ciscon et al.
patent: 5715184 (1998-02-01), Tyler et al.
patent: 5732247 (1998-03-01), Dearth et al.
patent: 5751941 (1998-05-01), Hinds et al.
patent: 5794005 (1998-08-01), Steinman
patent: 5812824 (1998-09-01), Dearth et al.
patent: 5838948 (1998-11-01), Bunza
patent: 5848236 (1998-12-01), Dearth et al.
patent: 5850345 (1998-12-01), Son
patent: 5870585 (1999-02-01), Stapleton
patent: 5875179 (1999-02-01), Tikalsky
patent: 5881267 (1999-03-01), Dearth et al.
patent: 5892957 (1999-04-01), Normoyle et al.
patent: 5907685 (1999-05-01), Douceur
patent: 5907695 (1999-05-01), Dearth
patent: 5910903 (1999-06-01), Feinberg et al.
patent: 5991533 (1999-11-01), Sano et al.
patent: 6031987 (2000-02-01), Damani et al.
patent: 6053947 (2000-04-01), Parson
patent: 6117181 (2000-09-01), Dearth et al.
patent: 6134234 (2000-10-01), Kapanen
patent: 6345242 (2002-02-01), Dearth et al.
patent: 6507809 (2003-01-01), Yoshino et al.
patent: 6675334 (2004-01-01), Wadley
patent: 6711411 (2004-03-01), Ruffini
patent: 6732068 (2004-05-01), Sample et al.
patent: 6748451 (2004-06-01), Woods et al.
patent: 2003/0093252 (2003-05-01), Frankel
patent: 2003/0093253 (2003-05-01), Freyensee
patent: 2003/0093254 (2003-05-01), Frankel
patent: 2003/0093255 (2003-05-01), Freyensee
patent: 2003/0093256 (2003-05-01), Cavanagh
patent: 2003/0093257 (2003-05-01), Cavanagh
patent: 2003/0093569 (2003-05-01), Sivier
patent: 2003/0229486 (2003-12-01), Ito
“Rule Base Driven Conversion of an Object Oriented Design Structure Into Standard Hardware Description Languages,” Verschueren, A.C., IEEE Xplore, appears in Euromicro Conference, 1998, Proceedings. 24th, vol. 1, Aug. 25, 1998, pp. 42-45.
“Modeling Communication with Objective VHDL,” Putzke, et al., IEEE Xplore, appears in Verilog HDL Conference and VHDL International Use Forum, 1998, IVC/VIUF, Proceedings., 1998 International, Mar. 16, 1998, pp. 83-89.
“A Procedural Language Interface for VHDL and its Typical Applications,” Martinolle, et al., IEEE Xplore, appears in Verilog HDL Conference and VHDL International Use Forum, 1998, IVC/VIUF, Proceedings, 1998 International, Mar. 16, 1998, pp. 32-38.
“The Verilog Procedural Interface for the Verilog Hardware Description Language,” Dawson, et al., IEEE Xplore, appears in Verilog HDL Conference, 1996, Proceedings., 1996 International, Feb. 26, 1996, pp. 17-23.
“An Integrated Environment for HDL Verification,” York, et al., IEEE Xplore, appears in Verilog HDL Conference, 1995, Proceedings, 1995 International, Mar. 27, 1995, pp. 9-18.
“The PowerPC 603 C++ Verilog Interface Model,” Voith, R.P., IEEE Xplore, appears in Compcon Spring '94, Digest of Papters, Feb. 28, 1994, pp. 337-340.
Networked Object Oriented Verification with C++ and Verilog, Dearth, et al., IEEE, XP-002144328, 1998, 4 pages.
Patent Abstracts of Japan, publication No. 10326835, published Dec. 8, 1998.
Patent Abstracts of Japan, publication No. 10049560, published Feb. 20, 1998.
Patent Abstracts of Japan, publication No. 10340283, published Dec. 22, 1998.
Patent Abstracts of Japan, publication No. 07254008, published Oct. 3, 1995.
“Multiprocessing Verilog Simulator Exploits the Parallel Nature of HDLs.” Lisa Maliniak, Electronic Design, Abstract, May 30, 1994, 1 page.
“It's A Multithreaded World, Part I,” Charles J. Northrup, BYTE, May 1992, 7 pages.
“It's A Multithreaded World, Part 2,” Charles J. Northrup, BYTE, Jun. 1992, pp. 351-356.
“Weaving a Thread,” Shashi Prasad, BYTE, Oct. 1995, pp. 173-174.
“Making Sense of Collaborative Computing,” Mark Gibbs, Network World Collaboration, Jan. 10, 1994, 4 pages.
“Parallel Logic Simulation of VLSI Systems,” Bailey, et al., ACM Computing Surveys, vol. 26, No. 3, Sep. 1994, pp. 255-294.
“Multithreaded Languages for Scientific and Technical Computing,” Cherri M. Pancake, Proceedings of the IEEE, vol. 81, No. 2, Feb. 1993, pp. 288-304.
“Distributed Simulation Architecture, SW Environment, Enterprise Server Products,” Purdue EE400 Presentation by Freyensee and Frankel, Nov. 9, 2000, 13 pages.
“BNF and EBNF: What Are They And How Do They Work?,” Lars Marius Garshol, Oct. 12, 1999, pp. 1-10.
“VCK: Verilog-C Kernel,” Testbench Automation, Distributed by Verilog Simulation, Hardware-Software Co-verification, 2001 Avery Design Systems, Inc., 8 pages.
“Principles of Verilog PLI,” Swapnajit Mittra, Silicon Graphics Incorporated, 1999, 10 pages.
“IEEE Standard Hardware Description Language Based on the Verilog® Hardware Description Language,” IEEE, Dec. 12, 1995, 8 pages.
“OpenVera 1.0, Language Reference Manual,” Version 1.0, Mar. 2001, pp. 4-1 to 4-34, pp. 5-1 to 5-32, 6-1 to 6-22, 7-1 to 7-24, 11-1 to 11-50, 12-1 to 12-8, 13-1 to 13-14, 14-1 to 14-20, 15-1 to 15-118.
“VLSI Designe of a Bus. Arbitration Module for the 68000 Series of Microprocessors,” Ososanya, et al., IEEE, 1994, pp. 398-402.
“A VHDL Standard Package for Logic Modeling,” David R. Coelho, IEEE Design & Test of Computers, vol. 7, Issue 3, Jun. 1990, pp. 25-32.
“Corrected Settling Time of the Distributed Parallel Arbiter,” M.M. Taub, PhD., IEEE Proceedings, Part E: Computers & Digitals, vol. 139, Issue 4, Jul. 1992, pp. 348-354.
“Quickturn Unveils Emulation and Prototyping Products,” Worldwide Videotex, vol. 13, Issue 7, p. 1-5, Jul. 1, 2000.
“Extreme-II,” Verisity Ltd., pp. 2, 2004.
“New Palladium II Extends Cadence Acceleration/Emulation Leadership,” Hehir, Kristin, Cadence Design Systems, Inc., pp. 2, Oct. 25, 2004.
“iProve AMBA Design Toolkit,” Dynalith Systems, pp. 2, Sep. 6, 2004.
“iProve Intelligent PROtotype Verification Engine,” Dynalith Systems Co., Ltd., pp. 2, 2001-2004.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Interfacing hardware emulation to distributed simulation... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interfacing hardware emulation to distributed simulation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interfacing hardware emulation to distributed simulation... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3984043

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.