Multiplex communications – Pathfinding or routing – Through a circuit switch
Utility Patent
1998-02-23
2001-01-02
Vu, Huy D. (Department: 2735)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S393000, C370S395430, C370S401000
Utility Patent
active
06169736
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an interfacing device for interfacing bit-parrallel data buses or different bit width and a control unit of the interfacing device, and a logical cell for use in such a control unit.
2. Discussion of Related Art
Such an interfacing device is already known in the art, e.g. from the U.S. Pat. No. 4,309,754, entitled ‘Data interface mechanism for interfacing bit-parallel data buses of different bit width’.
Therein (cf. Col. 1, In. 39-45), an interface mechanism is described which includes an incoming register means, named a data register, and a selection means, called a selector circuitry which connects portions of the data register to an outgoing data bus which is narrower than the data bus entering the data register. The selector circuitry in other words extracts outgoing sets of bits out of incoming sets of bits, the number of outgoing sets of bits being smaller than the number of incoming sets of bits.
Such an interfacing device is useful in particular when several data handling units are connected to the outgoing side of the interfacing device, and different ones of these data handling units need to be provided with only a portion of the data entering simultaneously the incoming side of the device. This is for instance so when the incoming sets of data bits are ATM (Asynchronous Transfer Mode) cell headers containing routing information only a portion of which is used to address a RAM (random access memory).
The selector circuitry described in U.S. Pat. No. 4,309,754 is drawn in
FIG. 1
of the U.S. Patent and consists of a microprocessor, control program storage means, a direct memory access controller, an interrupt controller, a dual port storage memory means, and some other means. The selector circuitry hence is very complex in hardware.
SUMMARY OF THE INVENTION
It is an object of the present invention to realize an interfacing device of the above known type, but wherein the hardware complexity of the selection means is reduced significantly.
According to a first aspect of the invention, an interfacing device (INT) to be coupled between an incoming channel (IC) and an outgoing channel (OC) and to be used to extract M outgoing sets of bits (OS
1
, OS
2
, . . . , OSM) out of N incoming sets of bits (IS
1
, IS
2
, . . . , ISN) received on said incoming channel (IC), M being an integer number smaller than N, said interfacing device (INT) comprising:
a. incoming register means (IR) provided to temporarily store said N incoming sets of bits (IS
1
, IS
2
, . . . , ISN); and
b. selection means (SEL) coupled between said incoming register means (IR) and said outgoing channel (OC), and provided to select M incoming sets of bits out of said N incoming sets of bits (IS
1
, IS
2
, . . . , ISN) and to route said M incoming sets of bits to said outgoing channel (OC) to thereby produce said M outgoing sets of bits (OS
1
, OS
2
, . . . , OSM),
is characterized in that said selection means (SEL) further comprises:
c. a multiplexing unit (MUX) including M multiplexers (MUX
1
, MUX
2
, . . . , MUXM), each multiplexer having a control input, N−M+1 input terminals adapted to sink N−M+1 incoming sets of bits out of said N incoming sets of bits (IS
1
, IS
2
, . . . , ISN), and one output terminal adapted to source one of said N−M+1 incoming sets of bits under control of a control signal applied to said control input; and
d. a control unit (CTRL) adapted to generate for said each multiplexer, said control signal and to apply said control signal via an output terminal of said control unit (CTRL) to said control input of said each multiplexer.
Indeed, when realizing the selector means only by a bank of identical multiplexers and a control unit, the hardware complexity is reduced significantly. Since the chip surface required to implement a multiplexer grows exponentially with the number of inputs and number of outputs thereof, a selector with a bank of identical multiplexers, each having N−M+1 inputs furthermore is less complex in hardware than a selector consisting of only one multiplexer having N inputs and M outputs. As will be seen later, the control unit for generating the control signals for the bank of multiplexers, can be realized with low hardware requirements.
It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being limitative to the means listed thereafter. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
Similarly, it is to be noted that the term “coupled”, also used in the claims, should not be interpreted as being limitative to direct connections only. Thus, the scope of the expression “a device A coupled to a device B” should not be limited to devices or systems wherein an output of device A is directly connected to an input of device B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means.
In further accord with the first aspect of the invention, the interfacing device is characterized in that a multiplexer with index i amongst said M multiplexers (MUX
1
, MUX
2
, . . . , MUXM), said N−M+1 input terminals are adapted to respectively sink incoming sets of bits with indices i to i+N−M amongst said N incoming sets of bits (IS
1
, IS
2
, . . . , ISN), and said output terminal of said multiplexer with index i is adapted to source an outgoing set of bits with index i amongst said M outgoing sets of bits (OS
1
, OS
2
, . . . OSM).
In this way, the sequence of outgoing sets of bits may respect the sequence of incoming sets of bits. This may be useful, as is indicated in Col. 1, In. 44 of U.S. Pat. No. 4,309,754. By applying sets
1
to N−M+1 to multiplexer
1
, sets
2
to N−M+2 to multiplexer
2
, . . . , sets M to N to multiplexer M, the outgoing sets of bits may be selected so that any couple of subsequent incoming sets of bits do not change order when passing through the interfacing device and thus become subsequent outgoing sets of bits if they are both extracted by the interfacing device.
In still further accord with the first aspect of the present invention, the interfacing device is characterized in that said control unit (CTRL) comprises: a matrix of identical logical cells (C
1,1
; . . . ; C
M,N−M+1
), each logical cell being associated with one multiplexer of said M multiplexers (MUX
1
, MUX
2
, . . . , MUXM) and with one input terminal of said N−M+1 input terminals of said one multiplexer, and being adapted to generate a control signal indicating whether said output terminal of said one multiplexer has to source an incoming set of bits sunk by said one input terminal or not.
Indeed, by constructing the control unit as a matrix of identical logical cells, the hardware complexity is even more reduced since the control unit is then realized by repeating a simple logical cell structure.
A particular embodiment of the interfacing device according to the first aspect of the present invention wherein the control unit is constructed of a matrix of logical cells is defined in that each logical cell is equipped with three input terminals (CB, ENJ+1) whereof:
a first input terminal (CB) is adapted to sink a signal indicating whether said incoming set of bits forms part of said M incoming sets of bits to be selected by said selection means (SEL);
a second input terminal (ENJ) is adapted to sink a signal indicating that said output terminal of said one multiplexer has to source an incoming set of bits sunk by another input terminal than said one input terminal;
a third input terminal (DISI) is adapted to sink a signal indicating that an outgoing terminal of another multiplexer than said one multiplexer has to source said incoming set of bits sunk by said one input terminal;
a first
Alcatel
Phan M.
Vu Huy D.
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