Interfacing between a physical layer and a bus

Details Interfacing between a physical layer and a bus Interfacing between a physical layer and a bus

1999-05-07

2004-11-30

Hsu, Alpus H. (Department: 2665)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S401000, C370S463000, C370S469000

Reexamination Certificate

active

06826187

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to computer networks. In particular, the invention relates to interfacing between a physical layer and a bus.
THE BACKGROUND OF THE INVENTION
Technologies for computer networks have advanced at a fast rate to accommodate the needs for efficient and reliable communication. Designs for computer networks are now becoming complex both in hardware and software. To reduce complexity, most computer networks are organized as a series of layers or protocols, each one built upon the one below it. The function of each layer is to provide certain services to the higher layers, shielding those layers from the specific and detailed implementation of these services.
A network architecture typically follows some reference model to maintain universality and standardization. Examples of important reference models include the broadband Integrated Services Digital Network (B-ISDN) Asynchronous Transfer Mode (ATM), the Open System Interconnection (OSI), and the Transmission Control Protocol/Internet Protocol (TCP/IP) reference models. In general, a network architecture has the following layers: application, transport, network, data link, and physical. In these layers, the actual data transmission takes place in the physical layer.
For ATM communications systems, the Universal Test & Operations PHY Interface for ATM (UTOPIA) parallel data interface is an industry standard for communications between an upper ATM layer module and a Physical Layer (PHY) module. Thus, vendors providing particular physical layer transceivers often include the PHY layer UTOPIA interface as part of their chipset functionality. In its most compact form, the minimum number of lines connecting to the ATM layer is 8 control and clock lines plus the number of data bus lines (8 or 16) with a bi-directional data bus at the ATM layer. Thus, for a UTOPIA interface with an 8-bit wide data bus, the minimum number of electrical pin connections between the PHY and ATM layer is 16.
Embedded systems for telecommunications often incorporate processors with an on-board or on-chip Communications Processor Module (CPM) with flexible capabilities including ATM functionality. Some CPMs include UTOPIA interface functionality while others do not. Most provide pins that perform different functions, depending on how the user assigns them. When a pin is assigned for one function, its other functions are not available. Thus, for a UTOPIA-capable CPM, when its pins are used in UTOPIA mode, the designer waives other functionality otherwise available on those pins. Given the number of pins consumed by the UTOPIA interface, this functionality loss can be significant. In a design in which the CPM does not include a UTOPIA interface, or one in which its UTOPIA interface is not used in order to preserve other functionality, a different means is necessary to connect it to the UTOPIA PHY.
Many CPMs include one or more serial communications controllers (SCC). A SCC might be programmed for time slot assigner (TSA) mode, in which case it is used as a TDM (Time Division Multiplexed) bus. Typically, a TDM bus requires only six pins, three for transmit and three for receive. Thus, a TDM bus interface requires significantly fewer pins than a UTOPIA interface.
SUMMARY OF THE INVENTION
A method and apparatus are described for interfacing between a physical layer (PHY) interface and a bus.
For the receiver side, the method comprises (a) receiving a downstream (DS) clock signal from a physical layer transceiver, (b) receiving a first plurality of PHY interface receiver signals from the PHY interface, and (c) generating bus receiver signals to the bus and a second plurality of PHY interface receiver signals to the PHY interface using the DS clock signal and the first plurality of PHY interface receiver signals.
For the transmitter side, the method comprises (a) receiving an upstream (US) clock signal from a physical layer transceiver, (b) receiving a first plurality of bus transmitter signals from the bus and a first plurality of PHY transmitter signals from the PHY interface, and (c) generating a second plurality of bus transmitter signals to the bus and a second plurality of PHY transmitter signals to the physical interface using the US clock signal, the one or more PHY transmitter signals and the one or more bus transmitter signals.
Other features and advantages of the invention will be apparent from the detailed description and drawings provided herein.


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