Interface with device having unusual access time and method ther

Details Interface with device having unusual access time and method ther Interface with device having unusual access time and method ther

1996-04-04

1998-09-15

Auve, Glenn A.

395733, 395856, G06F 1314

Patent

active

058092641

ABSTRACT:
An interface between a processor without ready or data acknowledge signal and a device having a remarkably slow or variable access time including: first and second latch terminals latching data and addresses; and a decoder controlling the latches and the flow of data. This interface is capable of lifting the restriction to usable devices to facilitate selection of processors or devices.

REFERENCES:
patent: 5432947 (1995-07-01), Doi
patent: 5502822 (1996-03-01), Takebe
patent: 5557757 (1996-09-01), Gephardt et al.

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