Interface with address decoder for selectively generating first

Details Interface with address decoder for selectively generating first Interface with address decoder for selectively generating first

1991-07-22

1995-04-25

Lee, Thomas C.

Boots, shoes, and leggings

395325, 395425, 395725, 3642457, 3642517, 3642599, 364DIG1, G06F 1502

Patent

active

054106540

ABSTRACT:
Interface circuitry for coupling to a microprocessor device. The interface circuitry includes an input for receiving address signal lines and control signal lines generated by the microprocessor device. The interface further includes an address decoder, responsive to the received address signal lines, for determining if a microprocessor-generated memory access is directed to a private memory, accessible only by the microprocessor device, or to a shared memory that is accessible by a plurality of microprocessor devices. Responsive to the address decoder, the interface circuitry provides first address signal lines and first control signal lines to the private memory in response to the microprocessor device generating a memory access to the private memory. Also responsive to the address decoder, the interface circuitry provides second address signal lines and second control signal lines for coupling to the shared memory in response to the microprocessor device generating a memory access to the shared memory. The interface circuitry further includes interrupt control circuitry, inter-processor interrupt circuitry, DMA circuitry, a serial bus interface, and also provides a plurality of miscellaneous functions for the microprocessor.

REFERENCES:
patent: 3573855 (1971-04-01), Cragon et al.
patent: 4080649 (1978-03-01), Calle et al.
patent: 4223380 (1980-09-01), Antonaccio et al.
patent: 4481580 (1984-11-01), Martin et al.
patent: 4484273 (1984-11-01), Stiffler et al.
patent: 4495575 (1985-01-01), Eguchi
patent: 4511969 (1985-04-01), Koenig et al.
patent: 4648034 (1987-03-01), Heninger
patent: 4663706 (1987-05-01), Allen et al.
patent: 4675811 (1987-06-01), Kishi et al.
patent: 4698753 (1987-10-01), Hubbins et al.
patent: 4737932 (1988-04-01), Baba
patent: 4843540 (1989-06-01), Stolfo
patent: 4872133 (1989-10-01), Leeland
patent: 4912633 (1990-03-01), Schweizer et al.
patent: 4928224 (1990-05-01), Zulian
patent: 4964033 (1990-10-01), Williams
patent: 5008817 (1991-04-01), Shibata et al.
patent: 5021950 (1991-06-01), Nishikawa
patent: 5115498 (1992-05-01), Maccianti et al.
patent: 5123101 (1992-06-01), Sindhu
patent: 5134700 (1992-07-01), Eyer et al.
patent: 5214776 (1993-05-01), Bagnoli et al.
patent: 5226134 (1993-07-01), Aldereguia et al.
patent: 5276850 (1994-01-01), Sakane
patent: 5305441 (1994-04-01), Okochi et al.

Affiliated with

Also associated with

Rating

Interface with address decoder for selectively generating first does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interface with address decoder for selectively generating first , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interface with address decoder for selectively generating first will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1574053