Interface unit facilitating data exchange between central proces

Details Interface unit facilitating data exchange between central proces Interface unit facilitating data exchange between central proces

1978-07-07

1980-06-24

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 300

Patent

active

042098416

ABSTRACT:
An interface unit, intervening in the high-speed transfer of data between an associated peripheral unit and a central memory of a processor, comprises a first and a second binary counter CM.sub.1, CM.sub.2 for the respective storage of memory addresses and of the number of data words to be read out from or written into a series of such addresses. In response to the arrival of an input/output instruction from a program memory of the processor, intended for the associated peripheral unit, a first sequential network RS' controls the loading of these counters with a starting address and an initial word count; if no other peripheral unit takes precedence, a second sequential network RS" then causes transmission of the contents of the first counter CM.sub.1, during successive cycles of a microroutine established by a control unit of the processor, to that processor followed by the readout (or write-in) of data words at the corresponding addresses, with incrementation of the address in counter CM.sub.1 and decrementation of the word count in counter CM.sub.2 at the end of each cycle. When the word count has been reduced to zero, network RS' emits a program-interruption request as a signal to the processor that the transfer has been completed.

REFERENCES:
patent: 4040026 (1977-08-01), Gernelle
patent: 4067059 (1978-01-01), Derchak
patent: 4115856 (1979-09-01), Labeye-Voisin et al.

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