Interface unit circuit with on-chip test simulation

Details Interface unit circuit with on-chip test simulation Interface unit circuit with on-chip test simulation

1993-03-17

1995-04-18

Voeltz, Emanuel T.

Multiplex communications

Wide area network

Packet switching

370 92, 371 221, G06F 1300

Patent

active

054086310

ABSTRACT:
A novel interface unit circuit for connecting circuit card assemblies to a data stream and to each other is designed for implementation on a high speed semiconductor chip. A parallel bit data word comprising a programmable address field is compared to a mask address stored in buffer registers and in the presence of a match, the parallel bit data word is stored in a sink register. Also the address field of the data word is filled with zeros and passed to the output of the data channel where the time slot for the data word may be written over with new data words or the time slot passed on to other circuit card assemblies or other elements.

REFERENCES:
patent: 5072377 (1991-10-01), Asai et al.
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5333269 (1994-07-01), Calvignac et al.

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