Patent
1996-01-11
1997-04-01
Beausoliel, Jr., Robert W.
39518501, 39518312, G06F 1100
Patent
active
056175345
ABSTRACT:
A computer system includes a microprocessor and an external cache memory coupled to the microprocessor. The cache memory includes a memory array and an apparatus for initiating a routine to test the integrity of the memory array in response to a signal asserted by the microprocessor. The apparatus generates a two-bit status signal coupled to the microprocessor for communicating IDLE, ACTIVE, PASS and FAIL states of the test routine. The apparatus initiates the test routine a predetermined of number clock cycles after the assertion of the signal provided by the microprocessor.
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"The Metaflow Architecture", pp. 10-13 and 63-73, by Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner, and David Isaman, IEEE Micro, 1991.
Balmer Mark J.
Waggoner Mark R.
Beausoliel, Jr. Robert W.
Intel Corporation
Palys Joseph E.
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