Interface port for electrically programmed fuses in a...

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S037000, C326S038000, C326S039000, C326S040000, C326S041000, C326S047000, C326S101000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07550324

ABSTRACT:
A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.

REFERENCES:
patent: 4703436 (1987-10-01), Varshney
patent: 6356095 (2002-03-01), Komoriya
patent: 7183801 (2007-02-01), Kao et al.
patent: 7243227 (2007-07-01), Knapp
patent: 7281082 (2007-10-01), Knapp
patent: 2004/0150426 (2004-08-01), Zhu et al.
patent: 2008/0309370 (2008-12-01), Spangaro
Xilinx, Inc.; “Virtex-4 FPGA Handbook”; Published Aug. 2, 2004; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 519-521.
Xilinx, Inc.; “Virtex-II Pro™ Platform FPGA Handbook”; Published Oct. 14, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 332-336.
Atmel, “32-megabit 2.7 volt DataFlash® AT45DB321C”; downloaded on May 24, 2006 from: //www.atmel.com/dyn/resources/prod—documents/doc3387.pdf; pp. 14.
Intel, “Intel StrataFlash® Memory (J3) Datasheet”; downloaded on May 24, 2006 from: //download.intel.com/design/flcomp/datashts/29066721.pdf; pp. 46-49.
Stephan Neuhold; XAPP694 (v1.0); “Reading User Data from Configuration PROMs”; Application Note; May 26, 2004; available from Xilinx, Inc. at www.xilinx.com; pp. 1-12.
Catalin Baetoniu et al.; XAPP780 (v1.0); “FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure EEPROMs”; Application Note; Aug. 17, 2005; available from Xilinx, Inc. at www.xilinx.com; pp. 1-6.
Xilinx, Inc.; U.S. Appl. No. 09/765,907 by Trimberger; filed Jan. 19, 2001 by Xilinx, Inc.
Xilinx, Inc.; U.S. Appl. No. 11/101,076 by Trimberger; filed Apr. 7, 2005 by Xilinx, Inc.
Xilinx, Inc.; U.S. Appl. No. 11/223,388 by Knapp; filed Sep. 9, 2005 by Xilinx, Inc.
Xilinx, Inc.; U.S. Appl. No. 11/450,755 by Walstrum et al.; filed Jun. 9, 2006 by Xilinx, Inc.
Xilinx, Inc.; U.S. Appl. No. 11/450,756 by Walstrum et al.; filed Jun. 9, 2006 by Xilinx, Inc.
Xilinx, Inc.; U.S. Appl. No. 11/449,935 by Walstrum et al.; filed Jun. 9, 2006 by Xilinx, Inc.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Interface port for electrically programmed fuses in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interface port for electrically programmed fuses in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interface port for electrically programmed fuses in a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4067478

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.