Interface for synchronous semiconductor memories

Details Interface for synchronous semiconductor memories Interface for synchronous semiconductor memories

1999-03-31

2001-03-06

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S051000, C365S063000

Reexamination Certificate

active

06198688

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor memories and in particular to an in improved interface and pin-out for synchronous semiconductor memories.
To improve the speed of memory circuits such as dynamic random access memories (DRAMs), a new generation of memory circuits has been developed that operates in response to a system clock. The system clock enables the memory circuit to operate synchronously with the associated controller. Thus, every read and write operation is synchronized with one edge, usually the rising edge, of the system clock. Referring to
FIG. 1
, there is shown a simplified block diagram of a prior art system using a single clock synchronous memory device
100
. A clock driver or generator
102
generates a clock signal CLK and supplies CLK to memory device
100
. A controller
104
connects to both memory device
100
and clock driver
102
. In existing systems, clock driver
102
is typically required to guarantee only the timing of the rising edge of the clock signal CLK which triggers the various operations of the system. There may be as much as 15% variation in the failing edge of CLK, resulting in a clock signal that does not have a 50% duty cycle. This is tolerable since all system activity is synchronized to the rising edge of CLK.
FIG. 2
is a timing diagram illustrating a read operation of the prior art single clock memory device. As shown, both the read command and the data outputs occur at rising edges of CLK signal while the falling edge which exhibits variations in its timing is essentially ignored. Therefore, given for example a CLK signal with a 10 ns period, the 15% variation in the falling edge leaves only about a 3.5 ns window for data processing.
The synchronous operation of the memory has improved the speed and bandwidth of the memory circuit by allowing the use of circuit techniques such as pipelining. However, given current microprocessors that operate much faster than the associated DRAMs, there is always a demand for faster memory chips with greater bandwidth.
SUMMARY OF THE INVENTION
The present invention provides various techniques and novel architectures for clocking synchronous memories that improve the overall speed and bandwidth of the memory circuit. Broadly, in one embodiment, the present invention provides a synchronous memory circuit that receives, and operates in response to, two clock signals that are complementary in nature. The provision of two clock pins that receive complementary clock signals as opposed to one results in a wider window of time for the memory circuit and the associated controller to process data and thus increases data bandwidth and signal integrity.
Another aspect of the present invention modifies the package pin-out for the synchronous memory circuit, moving a data strobe pin away from noisy pins, such as the pin receiving the clock signal, and closer to data pins. Further, the present invention provides a byte controllable data strobe scheme. According to this embodiment of the present invention, instead of a single data strobe signal, the memory circuit receives two or more strobe signals each dedicated to a selected sub-group of the data terminals.
Accordingly, in one embodiment, the present invention provides a semiconductor memory circuit including a first clock terminal coupled to receive a first periodic clock signal, a second clock terminal coupled to receive a second periodic clock signal, a first clock circuit coupled to the first clock terminal and configured to generate a first narrow pulse at one edge of the first clock signal; and a second clock circuit coupled to the second clock terminal and configured to generate a second narrow pulse at one edge of the second clock signal, wherein, a window of time for processing one data bit is defined by the temporal distance between the first narrow pulse and the second narrow pulse. In a more specific embodiment, the first periodic clock signal and the second periodic clock signal are complementary with respect to each other. Further, the first clock circuit generates the first narrow pulse on every rising edge of the first clock signal, and the second clock circuit generates the second narrow pulse on every rising edge of the second clock signal.
In another embodiment, the present invention provides a semiconductor memory device including a plurality of external pins adapted to interface with external circuitry, the plurality of external pins includes a plurality of data pins coupled to carry memory data, a clock pin coupled to carry a clock signal, a data strobe pin coupled to carry a data strobe signal, and a plurality of power pins, wherein the data strobe pin is located adjacent to a data pin and away from the clock pin. In a specific embodiment, the data strobe pin is located directly between a power pin and a data pin.
In yet another embodiment, the present invention provides a semiconductor memory device including a plurality of data pins coupled to carry memory data and divided into a first group and a second group, a first data strobe pin coupled to carry a first data strobe signal in response to which memory data on said first group of data pins is strobed, and a second data strobe pin coupled to carry a second data strobe signal in response to which memory data on said second group of data pins is strobed.


REFERENCES:
patent: 5812490 (1998-09-01), Tsukude
patent: 5880998 (1999-03-01), Tanimura et al.
patent: 5886948 (1999-03-01), Ryan
patent: 6064625 (2000-05-01), Tomita

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