Interface for processing element array

Details Interface for processing element array Interface for processing element array

1997-11-28

2000-07-04

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

712 16, 712 18, 712 11, 345100, H04N 5335, G06F 9345

Patent

active

060853042

ABSTRACT:
A memory-like I/O system is provided for interfacing a processing element array with a host system. The I/O system includes cornerturn logic for converting data written to the processing element array from horizontal format to vertical format and for converting data read from the processing element array from vertical format to horizontal format. Addressable interface memory is provided and includes a first bank for receiving and storing data which has been output from the cornerturn logic and for outputting that data for delivery to the processing element array. The addressable interface memory includes a second bank for receiving and storing data which has been output from the processing element array and for outputting that data for delivery to the cornerturn logic. The interface of the invention can provide support for concurrent I/O and processing, thereby allowing processing and I/O operations to proceed in parallel. The memory used to implement the interface can be used for on-chip paging to significantly reduce or eliminate the need for the slower and more costly off-chip paging.

REFERENCES:
patent: 4873630 (1989-10-01), Rusterholz et al.
patent: 5101371 (1992-03-01), Iobst
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5581773 (1996-12-01), Glover
patent: 5606707 (1997-02-01), Tomassi et al.

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