Interface for mailing system peripheral devices

Details Interface for mailing system peripheral devices Interface for mailing system peripheral devices

1983-09-15

1987-02-10

Thomas, James D.

Boots, shoes, and leggings

G06F 300

Patent

active

046427910

ABSTRACT:
An interface is connected between an OCIA type port and a mailing system peripheral, such as a weighing cell. The interface comprises an input data circuit, operatively connected to a serial data input line and to an associated input clock line, for receiving serial data input words comprising 8 serial data bits and an end-of-message (EOM) bit. The input circuit converts the serial input words into parallel form and transfers them to a programmable interface controller. The interface also includes an output circuit for transforming parallel output words from the interface controller into serial format. The output circuit is operatively connected to a serial data output line and an output data clock line from the OCIA type port. When an output data word is loaded into the output circuit the output line is forced to a predetermined logical level signalling the port the data is available. The port then provides a series of clock pulses to shift the data word out from the output circuit. When the data word is shifted out from the output circuit the circuit returns the output line to the initial state removing the data available signal. The programmable interface controller is responsive to a series of input words as messages from the OCIA type port. The interface controller is operatively connected to a weighing cell for providing weight and status information, and in response to a particular message, returns a message to the OCIA type port providing weight information and status information. In response to other messages, the programmable interface controller enters certain error routines, clears the interface to initial conditions, or resets the weighing cell to zero. The messages are provided in a predetermined format having header words descriptive of the meassage contents and ending in an error check word. The EOM bit of the error check word is of an opposite logical level from the EOM bit of the other words in a message and so indicates the end of the message.

REFERENCES:
patent: 3374467 (1968-03-01), Cast et al.
patent: 3975712 (1976-08-01), Hepworth et al.
patent: 4048673 (1977-09-01), Hendrig et al.
patent: 4065662 (1977-12-01), Garczynski et al.
patent: 4071887 (1978-01-01), Daly et al.
patent: 4168469 (1979-09-01), Parikh et al.
patent: 4272675 (1981-06-01), Blanford et al.
patent: 4395756 (1983-07-01), Daniels
patent: 4410961 (1983-10-01), Dlugos et al.
patent: 4410962 (1983-10-01), Daniels et al.
patent: 4527233 (1985-07-01), Ambrosius, III et al.
"Microprocessor Peripherals UPI User Manual", Intel, Apr. 1982, pp. 5-634 to 5-635.
"Optoelectronics Data Book", TRW, Jan. 1985, p. 184.
"The TTL Data Book, vol. 1", 1984, Texas Instruments, pp. 2-8, 3-621, 3-755, 3-888, and 5-3.
"Technical Aspects of Data Communication", by John E. McNamara, Jul. 1979; p. 43.
Functional Description of "MM54HC74/MM74HC74, Dual D Flip-Flop with Preset and Clear", National Semiconductor.

Affiliated with

Also associated with

Rating

Interface for mailing system peripheral devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interface for mailing system peripheral devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interface for mailing system peripheral devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2367284