Interface for accessing a wide-band bus handling speech and data

Multiplex communications – Wide area network – Packet switching

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370 94, H04J 302

Patent

active

045218820

ABSTRACT:
Each of several stations served by a common bus in a communication system of the packet-switching type has a layered structure interposed between a user terminal and a port giving access to the bus, this structure including an interface separating a transceiver at a bottom level of the structure from upper levels controlling the establishment, maintenance and termination of temporary signal paths for the transmission of data between stations. The interface is divided into a lower-tier portion, implemented by wired-logic circuitry, and a higher-tier portion, programmed to set up virtual point-to-point data links between its own station and other stations under the control of a microprocessor. The lower-tier portion dialogues with the transceiver and has transmitting and receiving sections with respective buffer memories for the temporary storage of outgoing message frames generated at the higher-tier portion and incoming message frames extracted from the bus and found to be addressed to the station involved. When an outgoing sequence consisting of one or more frames has been completely stored, or when the transmitting-side buffer memory is full, a logic unit in the transmitting section explores the probability of successful access to the bus with the aid of an algorithm based on a random numerical sequence different for several stations competing for access. When such access has been gained, the stored sequence is sent out. When an incoming sequence has been completely received, or when the receiving-side buffer memory is full, the contents of that memory are transferred to the higher-tier portion.

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"Software Error Checking Procedures for Data Communication Protocols", J. Wong et al, Computer Design, Feb. 1979, pp. 122-125.

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