Interface for a modularized computational unit to a CPU

Details Interface for a modularized computational unit to a CPU Interface for a modularized computational unit to a CPU

1995-04-28

1999-08-03

Maung, Zarni

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding by plural parallel decoders

712200, 712206, 712209, 712210, G06F 928, G06F 930, G06F 938

Patent

active

059319410

ABSTRACT:
A way of designing CPU's and computational units in an integrated circuit so that the computational unit can be designed and connected to the CPU in a modular manner. The computational unit designed for one application can be redesigned for another application without requiring a change in the CPU. The CPU has an instruction register, a first decoder connected to the instruction register to decode instruction words within a predefined set of instructions, an ALU, and buses which move operand data into the ALU and results data from the ALU. The ALU operates and the buses function responsive to the first decoder. The computational unit has an execution unit connected in parallel with the ALU to the buses, and a second decoder connected to the instruction register. The second decoder decodes only a predetermined portion of an instruction word in the instruction register when the instruction word is not in the predefined set of instructions. The execution unit operates responsive to the second decoder.

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