Interface conversion circuit

Details Interface conversion circuit Interface conversion circuit

1992-03-20

1994-06-21

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

375118, H04J 306

Patent

active

053233972

ABSTRACT:
The present invention relates to an interface conversion circuit for conversion of the frame structure of a first interface, such as a U-interface, into a second interface to ensure that the phase relation between frame clocks of both the first interface and the second interface is kept constant during communications by absorbing the jitter between the frame clocks of both interfaces when no certain phase relation is established between the frame clocks when the frame structure of the first interface is converted into the second interface. The interface conversion circuit according to the present invention includes a reception timing signal generator and second interface timing signal generator. The reception timing signal generator is adapted to shift the window signal WND and half window signal HWND, respectively, a predetermined number of bits ahead when the second interface frame clock MTC from the second interface timing signal generator lies in the former half of the window signal WND. The reception timing signal generator is adapted to shift the signals WND and HWND, respectively, a predetermined number of bits back when the second interface frame clock MTC from the second interface timing signal generator lies in the latter half of the window signal WND.

REFERENCES:
patent: 4392234 (1983-07-01), Maruta
patent: 4535452 (1985-08-01), Sandberg et al.
patent: 4811341 (1989-03-01), Fujimoto et al.
patent: 5162746 (1992-11-01), Ghoshal

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