Interface controller with first and second buffer storage area f

Details Interface controller with first and second buffer storage area f Interface controller with first and second buffer storage area f

1988-06-30

1991-03-26

Eng, David Y.

Boots, shoes, and leggings

3642285, 364238, 3642383, 364239, 3642394, 3642396, 3642397, 364240, 3642403, 3642513, 3642702, G06F 300, G06F 1300, G06F 1312, G06F 1516

Patent

active

050034634

ABSTRACT:
An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurallity of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.

REFERENCES:
patent: 4266281 (1981-05-01), Struger et al.
patent: 4271518 (1981-06-01), Birzele et al.
patent: 4322794 (1982-03-01), Kurakake
patent: 4371925 (1983-02-01), Carberry et al.
patent: 4396995 (1983-08-01), Grau
patent: 4442504 (1984-04-01), Dummermuth et al.
patent: 4466079 (1984-08-01), Daniels et al.
patent: 4475155 (1984-10-01), Oishi et al.
patent: 4523274 (1985-06-01), Fukunaga et al.
patent: 4527233 (1985-07-01), Ambrosius, III et al.
patent: 4528626 (1985-07-01), Dean et al.
patent: 4538224 (1985-08-01), Peterson
patent: 4604682 (1986-08-01), Schwan et al.
patent: 4644194 (1987-02-01), Birrittella et al.
patent: 4695948 (1987-09-01), Blevins et al.
patent: 4771191 (1988-09-01), Estrada
patent: 4809217 (1989-02-01), Floro et al.
patent: 4821179 (1989-04-01), Jensen et al.

Affiliated with

Also associated with

Rating

Interface controller with first and second buffer storage area f does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interface controller with first and second buffer storage area f, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interface controller with first and second buffer storage area f will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-622101