Interface controller for frame buffer random access memory devic

Details Interface controller for frame buffer random access memory devic Interface controller for frame buffer random access memory devic

1994-07-18

1996-11-26

Tung, Kee Wei

395446, 395449, 395509, 395515, G06F 1500

Patent

active

055794734

ABSTRACT:
A frame buffer memory device controller that schedules and dispatches operations to frame buffer memory devices is disclosed. The frame buffer memory device controller schedules and dispatches cache control operations to reduce timing overheads caused by cache prefetch operations, and operations to write back dirty cache lines and clear cache lines in the frame buffer memory devices. The frame buffer memory device controller also schedules and dispatches control operations to reduce timing overheads caused by video refresh operations from the frame buffer memory devices video output ports.

REFERENCES:
patent: 5185856 (1993-02-01), Alcorn et al.
patent: 5450542 (1995-09-01), Lehman et al.
patent: 5450563 (1995-09-01), Gregor

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