Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Reexamination Certificate
1999-04-13
2002-07-23
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
C345S558000, C345S538000
Reexamination Certificate
active
06424347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interface control apparatus for a frame buffer, and in particular to an improved interface control apparatus for a frame buffer which is capable of effectively performing a pixel data conversion between systems having different byte definitions and Endians.
2. Description of the Background Art
FIG. 1
illustrates an interface control apparatus for a conventional frame buffer which is disclosed in the U.S. Pat. No. 5,640,545.
As shown therein, a system bus
101
is formed of an address bus
103
and a data bus
105
. The system bus
101
is a 64-bit bus using a 8-bit as one byte and uses a big Endian data. In addition, the address bus
103
and data bus
105
mux the system bus
101
of 64-bit.
A processor
107
accesses the system bus
101
, and a main memory server system
109
controls a SRAM(Static Ramdom Access Memory), a DRAM(Dynamic Random Access Memory), a ROM(Read Only Memory), a cache memory, etc. In addition, an expansion bus
111
is a little bus capable of transmitting 32-bit data in parallel and is connected with a video input apparatus
113
.
The bridge/graphic controller
115
is one of the important elements of the conventional art includes a pixel unscramble logic
117
for judging whether or not a pixel data conversion is needed and performing a pixel data conversion and performs a data conversion and data transmission operation between the system bus
101
and the expansion bus
111
.
The frame buffer
119
stores a big Endian(BE) type pixel data to be displayed and includes a DRAM port
121
for communicating a pixel data with the bridge/graphic controller
111
, and a SAM(Serial Access Mode) port
123
accessing the pixel data stored in the frame buffer
119
and outputting to a RAM D/A converter(hereinafter called RAMDAC)
125
.
The RAMDAC(Random Access Memory D/A Converter)
125
is designed to receive a big Endian(BE) data and converts the digital data from the SAM port
123
into an analog data and outputs to a video output apparatus
127
.
Figure illustrate the bridge/graphic controller
111
.
As shown therein, multiplexers
203
,
205
,
207
,
209
,
211
,
213
,
215
,
217
,
219
and
221
and flip-flops
223
,
225
,
227
,
229
,
231
and
233
perform a switching operation and a buffering operation of each pixel data between the data bus
105
, the expansion bus
111
, and the frame buffer
119
.
The controller
253
generates various control signals for adjusting the operations of all elements in the bridge/graphic controller
115
, and the input/output byte swap multiplexers
249
and
251
performs an end-for-end byte swapping operation in accordance with the mode selection signal(BE mode or LE mode). In addition, the input/output byte swap multiplexers
249
and
251
form the constructions of the pixel unscramble logic
117
together with the byte rearranging logic
257
.
A FIFO(First-In-First-Out)
235
buffers the 64-bit wide data written from the data bus
105
into the expansion bus
111
, a FIFO
237
buffers a 64-bit wide data written from the data bus
105
or the frame buffer
119
into the expansion bus
111
.
A FIFO
245
buffers the 64-bit wide data from the data bus
105
into the frame buffer
119
, a FIFO
247
buffers the 64-bit wide data written from the expansion bus
111
into the frame buffer
119
.
A FIFO
243
buffers the 64-bit wide data read from the 64-bit buffer
119
and transmitted to the data bus
105
, and FIFO
239
and
241
buffers the 64-bit wide data transmitted from the expansion bus
111
to the data bus
105
.
The operation of the interface control apparatus for the conventional frame buffer will be explained.
The conventional interface control apparatus for the frame buffer is directed to a technique for transferring a frame buffer data between the system bus
101
, the expansion bus
111
using the little Endian, and the video output apparatus.
The bridge/graphic controller
115
provides an interface between the system bus
101
and the DRAM port
121
of the frame buffer
119
and receives a frame buffer access request from the system bus
101
and provides to the frame buffer
119
. In addition, the bridge/graphic controller
115
provides a path from the expansion bus is
111
to the frame buffer
119
and performs a bridge function for communication between the system bus
101
and the expansion bus
111
.
The bridge/graphic controller
115
performs a control operation in accordance with various control signals outputted from the controller
253
as shown in FIG.
2
.
Namely, the big Endian data inputted into the data bus
105
are converted into the little Endian data by the input byte swap multiplexer
249
in accordance with the mode selection signal, and the thusly converted little Endian data are stored into the FIFO
235
or the FIFO
237
and are outputted to the expansion bus
111
.
In addition, the little Endian data inputted from the expansion bus
111
is stored into the FIFO
239
or the FIFO
641
and is converted into a big Endian data by the output byte swap multiplexer
251
in accordance with the mode selection signal and is outputted to the data bus
105
.
At this time, the input byte swap multiplexer
249
as shown in
FIG. 3A
bypasses the pixel data at the data bus
105
when the mode selection signal is 0, and the pixel data at the data bus
105
is processed based on the end-for-end swapping when the mode selection signal
1
. In addition, as shown in
FIG. 3B
, the output byte exchange multiplexer
251
basically performs the same operation as the input byte exchange multiplex
249
.
The pixel unscramble logic
117
formed of the input/output byte swap multiplexers
249
and
251
and the byte rearranging logic
257
is controlled by a mode selection signal and pixel unscramble control signal. The above-described control signals are generated by the controller
253
in accordance with the mode (BE or LE mode) of the processor
107
, the pixel depths 32 bpp, 16 bpp, 8 bpp, and the transmitted pixel type.
In the information concerning the pixel type, the pixel data is decoded to a part of the pixel address indicating the position to be stored and searched from the frame buffer
119
, and the information with respect to the mode of the processor
107
, and the pixel depth is provided from the process
107
to the controller
253
at the initialization stage of the system and is stored into the control register
253
a.
The bridge/graphic controller
115
converts the big Endian data inputted through the data bus
105
into the little Endian data through the input byte swap multiplexer
249
and stores into the FIFO
245
and unscrambles the pixel data using the byte rearranging logic
257
and then the thusly unscrambled data are outputted to the frame buffer data bus
201
or the data inputted from the expansion bus
111
into the FIFO
247
, and the pixel data are unscrambled by the byte rearranging logic
257
and are outputted to the frame buffer data bus
201
.
In addition, the bridge/graphic controller
115
unscrambles the data read from the frame buffer
119
through the byte rearranging logic
257
and stores into the FIFO
237
and outputs to the expansion bus
111
or stores into the FIFO
243
. The little Endian data are converted into the big Endian data by the output byte swap multiplex
251
and are outputted to the data bus
105
.
At this time, as shown in
FIG. 4
, the byte rearranging logic
657
includes a frame buffer input multiplexer
257
a
rearranging the pixel data written into the frame buffer
119
in accordance with a pixel unscramble control signal outputted from the controller
253
, and a frame buffer output multiplexer
257
b
rearranging the pixel data read from the fame buffer
119
in accordance with a pixel unscramble control signal outputted from the controller
253
.
The frame buffer input multiplexer
257
a
performs a data conversion during the write operation of the frame buffer
119
in which the frame buffer(FB) read signal is disabled, and
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Tung Kee M.
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