Interface comprising message and protocol processors for interfa

Details Interface comprising message and protocol processors for interfa Interface comprising message and protocol processors for interfa

1985-12-17

1989-08-15

Zache, Raulfe B.

Boots, shoes, and leggings

370 85, 370 16, 364239, 3642397, 364228, 3642425, 3642433, G06F 300, G06F 928, G06F 1312, G06F 1516

Patent

active

048581127

ABSTRACT:
A network interface equipment for a bus network employs separate processors and random-access memories for handling bus-protocol and data portions of a data packet. Each processor has access to a separate random-access memory to and from which it moves data. The random-access memories are multiple-ported to permit access by more than one requester with a logic arbitrator to resolve conflicts. A status random-access memory provides communication between the two processors.

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