Interface circuit with high speed data transmission

Details Interface circuit with high speed data transmission Interface circuit with high speed data transmission

1998-07-13

2000-03-21

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327141, H04L 700

Patent

active

060407239

ABSTRACT:
An interface circuit with high speed data transmission is disclosed. The interface circuit comprises a clock signal generator outputting a clock signal and an inversion clock signal, a shift signal generator receiving a start signal, the clock signal and the inversion clock signal. The shift signal generator outputs shift signals having odd shift signals and even shift signals. A first signal of the odd shift signals is generated in response to the start signal and the clock signal. The even shift signal is generated in response to a previous odd signal and the inversion clock signal. The odd shift signal is generated in response to a previous even signal and the clock signal. The interface circuit further comprises a data distribution circuit and odd and even output circuits. The data distribution circuit receives data, the clock signal and the inversion clock signal and outputs odd data in response to the data and the clock signal and even data in response to the data and the inversion clock signal. The odd data output circuit receives the odd data and outputs the received data in response to the odd signal. The even data output circuit receives the even data and outputs the received data in response to the even signal.

REFERENCES:
patent: 5022057 (1991-06-01), Nishi et al.
patent: 5886552 (1999-03-01), Chai et al.

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