Interface circuit of various clock period between a fast...

Details Interface circuit of various clock period between a fast... Interface circuit of various clock period between a fast...

2002-05-30

2003-11-04

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S274000, C327S287000, C375S376000, C331SDIG002

Reexamination Certificate

active

06642761

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an integrated circuit of a semiconductor memory, and more particularly to an interface circuit between a clock input signal and delay cells of a delay lock loop.
2. Description of the Prior Art
Major design efforts have been directed at circuit design techniques involving clock input signals and voltage controlled delay lock loop (DLL) circuits.
A number of solutions have been proposed.
U.S. Pat. No. 6,137,327 (SchneII) describes a delay lock loop circuit, which includes a receiver for receiving a system clock signal. Its output is a first clock signal derived from the system clock signal. It includes a delay lock loop for receiving the first clock signal, which synchronizes the delay lock loop. It also includes a phase detector and an off chip driver circuit for receiving the first clock signal. Its data output is in accordance with a second clock signal derived from the first. There is a feedback loop which couples the off chip driver to the phase detector. This loop includes an on chip delay circuit and a package delay circuit, both used for modeling purposes. The system clock signal is synchronized with the off chip driver output by means of the feedback loop.
U.S. Pat. No. 6,150,856 (Morzano) discloses delay lock loops, signal-locking methods, and methods of implementing delay lock loops. There is discussion of a delay lock loop comprised of a delay line having two inputs, a clock signal and an input coupled to the delay line output, and an output clock signal, set by the delay lock loop. There is also a phase detector whose output is coupled with the input of the delay line. Delay elements are configured to provide additional delay to the phase detector.
U.S. Pat. No. 6,229,368 (Lee) shows an integrated circuit for generating local clock signals with no phase difference from an internal clock signal. It also shows an internal clock generating circuit, which generates a signal with reduced sensitivity to process, temperature, voltage, and noise. The generating circuit for the local clock signals includes several phase blenders. The internal clock generating circuit includes a feedback circuit and a delay lock loop circuit. The feedback circuit generates a feedback clock signal. The delay lock circuit receives this signal, as well as an external clock signal, and generates the internal clock.
There is further need to improve the performance of semiconductor memory devices by providing operation at different clock frequencies, specifically by which an integrated circuit can generate an internal clock signal from a fast slope clock input, to be used as an input to the low frequency operation of a delay cell, in a delay lock loop.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a wide band interface circuit between a very fast slope clock signal input and a very slow slope voltage controlled delay cell of a delay lock loop, while keeping the same amplitude when the slope is changed.
It is a further object of the invention to provide a means for generating the internal clock signal to track the slope of each delay stage, whether it is at a higher frequency for which the slope of the delay stage is faster or at a lower frequency for which the slope of the delay stage is slower.
These and other objects are achieved by an integrated circuit that includes: a voltage bias portion for PMOS VBP and NMOS VBN; an analog clock input portion for clock signals IP and IN; circuit devices for interfacing with different clock frequency inputs (N
31
, N
32
and P
31
, P
32
); and an output portion for producing clock signals ON and OP. Furthermore, the invention may be used to change the slope of the input signal of a delay lock loop, where multiple delay stages are used and the delay of each stage is varied.


REFERENCES:
patent: 5012142 (1991-04-01), Sonntag
patent: 5731727 (1998-03-01), Iwamoto et al.
patent: 5869992 (1999-02-01), Sekino
patent: 6137327 (2000-10-01), Schnell
patent: 6150856 (2000-11-01), Morzano
patent: 6229368 (2001-05-01), Lee
patent: 6407601 (2002-06-01), Lin

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