Interface circuit, memory interface system, and data...

Details Interface circuit, memory interface system, and data... Interface circuit, memory interface system, and data...

2011-01-04

2011-01-04

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S233160, C365S233100, C365S193000, C365S194000

Reexamination Certificate

active

07864626

ABSTRACT:
An interface circuit includes a delay circuit that generates a delay signal obtained by delaying a data strobe signal, a first logical circuit that performs a logical operation of on the data strobe signal and the delay signal, and outputs an operation result as a first strobe signal, a second logical circuit that receives the first strobe signal and generates a second strobe signal that is complementary to the first strobe signal; a first latch circuit that latches a data signal based on the first strobe signal, and a second latch circuit that latches the data signal based on the second strobe signal.

REFERENCES:
patent: 4063244 (1977-12-01), Van de Kop
patent: 5896347 (1999-04-01), Tomita et al.
patent: 6330636 (2001-12-01), Bondurant et al.
patent: 2002/0122348 (2002-09-01), Lee et al.
patent: 2002/0176447 (2002-11-01), Marx et al.
patent: 2004/0217386 (2004-11-01), Lee

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