Interface circuit for signal generators with two non-overlapping

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307246, 307262, 307265, 307270, 307578, H03K 3353, H03K 3017, H03K 5156, H03K 505

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active

045874417

ABSTRACT:
An interface circuit with MOS-type transistors for timing signal generators with two non-overlapping phases made up of two identical twin circuits, each having a final stage of the type including two transistors connected in series between the two terminals of a supply voltage generator and a bootstrap capacitor. Each of the two twin circuits includes a logic NOR circuit and a logic AND circuit which control, respectively, the charging and discharging of the capacitor through a suitable switching circuit connected to both terminals thereof. In each circuit, a memory circuit element is connected to the logic circuits. The memory circuit element is sensitive to the output signals of both twin circuits and enables the charging and discharging of the bootstrap capacitor at successive, logically produced time intervals which occur between the pulses of the output signals of both twin circuits.

REFERENCES:
patent: 3927334 (1975-12-01), Callahan
patent: 3961269 (1976-06-01), Alvarez, Jr.
patent: 3986046 (1976-10-01), Wunner
patent: 4230951 (1980-10-01), Suzuki et al.
patent: 4283639 (1981-08-01), Roesler
patent: 4291240 (1981-09-01), Rosler
patent: 4456837 (1984-06-01), Schade, Jr.
Cassidy et al., "Dynamic MOSFET Logic Clock Driver", IBM Tech. Discl. Bull.; vol. 22, No. 3, pp. 1093-1094; 8/79.

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