Interface circuit for semiconductor memory device

Details Interface circuit for semiconductor memory device Interface circuit for semiconductor memory device

1991-08-14

1993-03-09

Dzierzynski, Paul M.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307140, 307126, H03K 190175

Patent

active

051928833

ABSTRACT:
Disclosure herein is an interface circuit for a semiconductor memory device, which is so structured that, when a control signal (VBC) is supplied to a control signal input end, a transistor (2) first enters a conducting state to supply a supply voltage to a semiconductor memory device (1) and thereafter bus control means (7, 8) is brought into a conducting state by a control signal delayed by a delay circuit (22), to supply bus signals (ADD', CTD' and DTS') to the semiconductor memory device.

REFERENCES:
patent: 4300213 (1981-11-01), Tanimura
patent: 4682052 (1987-07-01), Kyomasu
patent: 4763303 (1988-08-01), Flannagan
patent: 4882506 (1989-11-01), Johansson

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