Interface circuit for high speed data transfer between a periphe

Details Interface circuit for high speed data transfer between a periphe Interface circuit for high speed data transfer between a periphe

1993-12-16

1995-04-18

Bowler, Alyssa H.

Boots, shoes, and leggings

364DIG1, 364238, 3642386, 364239, 395250, G06F 300

Patent

active

054086787

ABSTRACT:
An interface circuit which is connected between a peripheral device and a computer and which can conduct a data transfer at a higher speed. When a first digital data D.sub.1 is output from a peripheral device, the transfer of a memory bus enable request signal DRQ to a computer is halted by transfer control means, and the first digital data is output from the peripheral device in accordance with a false read control signal FIOR from an interface circuit, and held in hold means. When a second digital data is output from the peripheral device, DRQ is transferred to the computer, and 2N-bit data, i.e., N-bit second digital data D.sub.2 output from the peripheral device, and the N-bit first digital data D.sub.1 which is held are simultaneously transferred to the computer in accordance with a read control signal IOR from the computer.

REFERENCES:
patent: 4210959 (1980-07-01), Wozniak
patent: 4802152 (1989-01-01), Marvoort et al.

Affiliated with

Also associated with

Rating

Interface circuit for high speed data transfer between a periphe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interface circuit for high speed data transfer between a periphe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interface circuit for high speed data transfer between a periphe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-75029