Interface circuit for controlling data transfers

Details Interface circuit for controlling data transfers Interface circuit for controlling data transfers

1992-11-25

1995-10-17

Harvey, Jack B.

395853, 395868, G06F 1314

Patent

active

054598702

ABSTRACT:
In a computer system including a host which operates in a pre-read mode to start a block data transfer after reading status of a peripheral device (HDD) in response to an interrupt from the peripheral device or in a post-read mode to read the status after completing the block data transfer, an interface circuit comprising mode detecting circuitry for automatically detecting whether the host operates in the pre-read mode or in the post-read mode so that data transfers can be correctly performed between the peripheral device and the host even if the host is in either mode, delay circuitry for delaying by a predetermined amount of time, a data request DRQ indicating that a block of data is ready to be transferred, when the post-read mode is detected, and interrupt circuitry for sending an interrupt request IRQ to the host in response to the output of the delay circuitry.

REFERENCES:
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patent: 4086627 (1978-04-01), Bennett et al.
patent: 4268906 (1981-05-01), Bourke et al.
patent: 4456970 (1984-06-01), Catiller et al.
patent: 4847752 (1989-07-01), Akashi
patent: 5038275 (1991-08-01), Dujari
patent: 5150465 (1992-09-01), Bush et al.
patent: 5274795 (1993-12-01), Vachon

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