Interface circuit for asychronous data transfer

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307480, 307269, 328 63, 328 72, 377 78, H03K 190175, H03K 1900, H03K 301

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active

050121383

ABSTRACT:
An interface circuit connected between first and second units includes first and second registers, wherein these first and second units are asynchronous with each other. Data from the first unit is written into the first register by a write pulse from the first unit, while the output of first register is to be read by the second register by a read-in pulse from the second unit. This write pulse is asynchronous with the read-in pulse. When a phase difference between phases of the write pulse and read-in pulse is within the predetermined phase range, the phase of read-in pulse is varied by the predetermined phase value, e.g., 180 degrees. Then the second register reads in the output of first register by this read-in pulse whose phase is varied. Thereafter, the output of second register is fed to the second unit, so that the data transfer is performed between the first and second units without data dropout.

REFERENCES:
patent: 3893033 (1975-07-01), Finch
patent: 4341950 (1982-07-01), Kyles et al.
patent: 4525849 (1985-06-01), Wolf
patent: 4649512 (1987-03-01), Nukiyama
Adams, "Sequential Buffer Control", IBM Tech Disclosure Bulletin, vol. 14, No. 7, Dec. 1971, pp. 2069-2070.

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