Interface circuit for a differential signal

Details Interface circuit for a differential signal Interface circuit for a differential signal

2002-02-19

2003-06-17

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S253000, C330S261000, C330S300000

Reexamination Certificate

active

06580323

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a circuit comprising a first and a second input for receiving a differential signal and a buffer circuit, which buffer circuit comprises an input stage with a first and a second differential amplifier, a first current source for supplying a first current of a first polarity to the first differential amplifier, a second current source for supplying a second current of opposite polarity to the second differential amplifier, in which each of the differential amplifiers has a first input coupled to the first input of the circuit and a second input coupled to the second input of the circuit, a combination stage comprising at least one chain with a first node coupled to an output of the first differential amplifier and a second node coupled to an output of the second differential amplifier, and an active circuit, a main current path of which is coupled between the first and the second node, a control electrode of said active circuit being coupled to a bias voltage.
2. Description of the Related Art
Such a circuit is known from U.S. Pat. No. 5,703,532. Said patent discloses a differential signal amplifier having a rail-to-rail common-mode input voltage range. It is not known whether the gain for small signals of the entire circuit is constant over the entire common-mode range. Furthermore, said circuit is built up entirely of field effect transistors, which imposes limits as regards the highest frequencies that can be handled. SUMMARY OF THE INVENTION
It is an object of the invention to provide a circuit, which exhibits a substantially constant gm signal gain for small signals over the entire common-mode range and which is capable of handling high frequencies.
In addition, it is an object of the invention to provide a circuit for a differential signal amplifier, which is capable of handling the current standards (P)ECL, CML and LVSD. One common feature of these standard interfaces for high speeds is, among other things, the fact that they are differential, that a transmission line interface is provided, that is, generally 50 Ohm turn-off (or 100 Ohm differential), that the voltage swing is limited (200 mV . . . 800 mV diff) and that there is a defined hysteresis on the input. The differences mainly reside in the common-mode signals levels: CML level is substancially equal to a level of the positive rail, LVDS level is substancially equal to a level of the negative rail and (P)ECL level is lower than a level of the positive rail e.g. circa 1.3 V. LVDS is the most recent of said standards. LVDS is a data interface standard which is defined in the TIA/EIA-644 and the IEEE 1596.3 standards. The LVDS standard is used for high-speed transmission of binary data over copper conductors. The voltage swing is smaller than that of other transmission standards. Because of this small voltage difference, the data transmission speed is higher and an inherently larger bandwidth is obtained with a lower power consumption. In addition, LVDS produces less electromagnetic interference than other transmission standards.
Another object of the invention is to provide an interface circuit that can suitably function as an input stage in systems in which signals are transmitted in the form of differential signals that comply with the LVDS standard.
In order to accomplish that objective, a circuit according to the invention is wherein the active circuit comprises a single transistor, the bias voltage is a fixed voltage, and at least one of the two outputs to which a node is coupled, is an output of the buffer circuit.
As a result, the input signals can be differential signals, with the common-mode being capable of moving from rail-to-rail and a high degree of constancy of the gain over the entire common-mode range being obtained.
A preferred embodiment of a circuit according to the invention is wherein a hysteresis adding circuit is coupled to an output of the buffer circuit.
The hysteresis adding circuit enables precise determination of the degree of hysteresis that the circuit can accept. This is in particular important in the case of the LVDS standard, in which 25-millivolt hysteresis on the input of the circuit must be possible.


REFERENCES:
patent: 5515003 (1996-05-01), Kimura
patent: 5525930 (1996-06-01), Pothast et al.
patent: 5552742 (1996-09-01), Perkins
patent: 6188280 (2001-02-01), Filip

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