Patent
1994-11-07
1998-02-10
Harvey, Jack B.
395309, 395824, 395854, 395872, 395891, G06F 1300
Patent
active
057179484
ABSTRACT:
An interface circuit disposed between a processor and a peripheral device to facilitate the transfer of data therebetween. The interface circuit includes at least one buffer memory connected firstly to the data bus of the processor and secondly to the parallel port of a conversion register whose series port is connected to the peripheral device. A counter generates a first address and a first memory access control signal given to a selection circuit that also receives a second address and a second memory access control signal coming from the processor. Depending on a selection signal, the circuit sends either the first address and the first control signal or the second address and the second control signal to the buffer memory. Thus, data transferred between the processor and the peripheral is passed through the buffer memory.
REFERENCES:
patent: 4807121 (1989-02-01), Halford
patent: 5124980 (1992-06-01), Maki
patent: 5138611 (1992-08-01), Carn et al.
patent: 5163132 (1992-11-01), DuLac et al.
patent: 5208913 (1993-05-01), Yamamoto
patent: 5228129 (1993-07-01), Bryant et al.
patent: 5448701 (1995-09-01), Metz, Jr. et al.
Etienne Ario
Giunta Richard F.
Harvey Jack B.
Morris James H.
SGS-Thomson Microelectronics S.A.
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