Interface circuit arrangement for transferring data from a maste

Details Interface circuit arrangement for transferring data from a maste Interface circuit arrangement for transferring data from a maste

1983-01-17

1987-10-13

Williams, Jr., Archie E.

Boots, shoes, and leggings

371 9, 364132, 364187, G06F 1516, G06F 1116, G06F 1200

Patent

active

047002921

ABSTRACT:
Two identical processors of a communication system, operating in master-slave relationship, each have a mass memory, a working memory, a CPU and an interface interlinked by an internal bus, the two interfaces being interconnected by an interprocessor bus serving for the exchange of data therebetween. When the mass memory of the slave process or needs updating, data words to be transferred from the mass memory of the master processor are fed via the interprocessor bus and a buffer store of the slave processor to the working memory thereof from which they are subsequently delivered to the associated mass memory while the CPU of the master processor performs other operations. A block of data words thus transferred is preceded by a header, emitted by the master CPU, which sets a word counter in the associated interface whose progressive decrementation determines the end of the transfer operation. Outgoing words are supplemented in the master interface with redundancy bits enabling correction of possible errors upon their arrival at the slave interface.

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