Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-06-28
2001-11-27
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185090
Reexamination Certificate
active
06324096
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an interface circuit and method for programming a non-volatile memory, and to a type of scan register useful in this circuit.
Non-volatile memory is a basic component of many integrated-circuit devices, including so-called ‘system-on-a-chip’ devices. Such devices often use a reprogrammable type of non-volatile memory, such as electrically erasable and programmable read-only memory (EEPROM), or flash memory (also referred to as flash ROM). Flash memory, which is electrically erasable in large blocks, is often used to store program code and parameter data in microcontroller chips, and in system-on-a-chip devices having a microcontroller core.
One advantage of flash memory in these devices is that it enables software changes to be implemented and tested with very short turn-around times, even enabling devices installed on printed-circuit boards to be reprogrammed in the field. For devices with large system programs, on-board reprogramming has become an essential capability, as it is virtually impossible to foresee all eventualities during the software design stage. Reprogrammability is useful for debugging, for customizing devices to user specifications, for updating parameters and other data stored in tables, and for extending the life cycle of a device or system through frequent software revisions.
minimize the number of LSI terminals needed to implement the interface protocol, reprogramming is usually carried out through a serial interface circuit. Different manufacturers have used different serial interfaces, including the one described in IEEE Standard 1149.1-1990, which specifies a standard test access port and boundary-scan architecture. This interface standard is also known as JTAG revision 2.0, because of developmental work done by the Joint Test Action Group, and the associated technology is often referred to as JTAG technology.
Incidentally, LSI stands for large-scale integrated circuit, and IEEE for the Institute of Electrical and Electronics Engineers.
A device employing JTAG technology has a test access port (TAP) with a test data input terminal, a test data output terminal, and boundary scan circuits chained serially between these two terminals, enabling the input and output signals of the device to be observed and manipulated inside the device. If multiple devices of this type are mounted on the same printed-circuit board, their test access ports can be linked together to form a single boundary scan chain providing test access to all of the devices, enabling both internal device functions and interconnections between the devices to be tested.
Recently, JTAG technology has also been used as an interface for debugging the software of the microcontroller core of a system-on-a-chip, by providing a debugging scan chain, separate from the boundary scan chain, between the test data input and output terminals. It would be convenient if the same interface could also be used to program flash memory in the chip, so that debugging and reprogramming could be carried out in the same environment simply by connecting a debugger and a terminal device to the test access port, without the need for special equipment or wiring. Similarly, manufactured products could be programmed with customized software and then tested, using the same test access port for both purposes. A specialized flash-memory programming device, referred to below as a flash programmer, could also be connected to the test access port for on-board reprogramming in the field.
Aside from convenience, using the same test access port for debugging, programming, and testing is a way to reduce system costs.
A conventional way to enable on-chip flash memory to be programmed through the JTAG test access port is to provide a separate chain of memory-access registers between the test data input and output terminals. The memory-access register chain needs to include an address register for supplying address signals to the flash memory, a data register for storing read and write data, and a control register for supplying control signals to the flash memory. In the conventional scheme, these three registers are connected serially, the output data of one register becoming the input data of the next register in the chain.
A problem with the conventional memory-access register chain is that to read or write each word of flash-memory data, the associated address signals and control signals, as well as the data, must be shifted into or out of the memory-access registers. Input data destined for the register farthest from the test data input terminal must first be shifted through the other two registers. The total number of shift operations that must be performed per read or write access is therefore equal to the combined bit length of the address, data, and control registers.
The shift operations are synchronized with a test clock signal, which is supplied from the flash programmer or other host device that accesses the flash memory. The test clock frequency is limited, typically to one megahertz or less, because of the presence of electrical noise and other disturbing factors. The flash memory may have a capacity of several hundred kilobytes. Transferring this amount of data through a conventional register chain, with a test clock frequency of one megahertz or less, can easily take more than a minute. This delay is inconvenient during debugging, and intolerable in factory tests and inspections.
A further problem is that flash-memory storage capacity, sector size, and word width differ from one device to another. Consequently, the bit lengths of the address and data registers in the memory-access scan chain differ from one device to another. As new devices are constantly being developed, it is impractical to provide a flash programmer with pre-stored information describing the flash-memory parameters of every device that might need to be programmed. The alternative is to enter this information manually when the flash programmer is used, or to use different flash programmers for different types of devices, but both of these procedures are inconvenient and invite errors such as inadvertent entry of incorrect data or use of the wrong flash programmer.
An example of a conventional memory-access register chain and a more detailed description of these problems will be given later.
SUMMARY OF THE INVENTION
An object of the present invention is to speed up serial access to a non-volatile memory disposed in an integrated circuit.
Another object of the invention is to enable automatic set-up of a communication protocol between the integrated circuit and a programming device.
Yet another object is to increase the amount of parallel parameter data that can be captured and scanned out by a scan register.
The invented interface circuit comprises a plurality of memory-access scan registers coupled in common to a data input terminal of an integrated circuit in which the non-volatile memory is disposed, receiving serial data related to access to the non-volatile memory from the data input terminal. The interface circuit also has at least one selection scan register coupled to the data input terminal, receiving a code selecting at least one of the memory-access scan registers, and has at least one multiplexer coupling the memory-access scan registers and selection scan register to a data output terminal of the integrated circuit, for serial output of data from these registers.
The memory-access scan registers include, for example, a data register storing data to be written in the non-volatile memory, an address register storing address information for the non-volatile memory, a function command register storing a code for controlling the non-volatile memory, and a profile register. The profile register captures parallel parameter data from the integrated circuit for serial output at the data output terminal. The parallel parameter data may include various parameters of the non-volatile memory.
The interface circuit may also have an instruction register to which instruction codes are provid
Nguyen Tan T.
OKI Electric Industry Co., Ltd.
Volentine & Francos, PLLC
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