Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2009-03-16
2010-11-30
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230080, C365S189011
Reexamination Certificate
active
07843760
ABSTRACT:
Interface circuitry is provided for coupling between a memory device and processing circuitry, the processing circuitry issuing a plurality of access signals relating to accesses to be performed in the memory device. The interface circuitry comprises write address latch circuitry for storing a write address signal, and write address decoder circuitry that is responsive to a set first enable signal to decode the write address signal provided from the write address latch circuitry. Further, read address latch circuitry is provided for storing a read address signal issued by the processing circuitry, and read address decoder circuitry is responsive to a set second enable signal for decoding the read address signal provided from the read address latch circuitry. Decoder select latch circuitry is responsive to an access type indication signal from the processing circuitry to generate the first and second enable signals in dependence on that access type indication signal. In the event of metastability occurring in the decoder select latch circuitry, the decoder select latch circuitry is arranged not to set at least the second enable signal, thereby disabling at least the read address decoder circuitry in the presence of such metastability. Such an approach prevents metastable signals being used in the arbitration of data accesses in a manner which could corrupt the state of the memory device.
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Bull David Michael
Das Shidhartha
ARM Limited
Hoang Huan
Nixon & Vanderhye P.C.
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