Interface circuit and interface circuit delay time controlling m

Details Interface circuit and interface circuit delay time controlling m Interface circuit and interface circuit delay time controlling m

1997-09-24

2000-06-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327149, 327158, 327271, H03H 1126

Patent

active

060811463

ABSTRACT:
An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal. A phase difference detection circuit receives an output signal of a flip-flop provided on an output end of a data line of the integrated circuit and an output signal of the phase difference compensation circuit, detects phase difference between both output signals and outputs the control signal in response to the phase difference.

REFERENCES:
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5638019 (1997-06-01), Frankeny
David Bell, Solid state pulse circuits, second edition, Prentice Hall, pp. 271-273, 1981.

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