Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2008-05-20
2008-05-20
Phan, Trong (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000
Reexamination Certificate
active
07376043
ABSTRACT:
An interface circuit includes: a first synchronizing circuit for synchronizing a signal having a delay equal to or more than a predetermined period with respect to a reference clock, with the reference clock; a second synchronizing circuit for synchronizing a signal having a delay less than the predetermined period with respect to the reference clock, with the reference clock; a delay determining circuit for outputting a determination signal based on a delay of the signal relative to the reference clock; a delay determination setting circuit for outputting a path setting signal that designates an output value of one of the first synchronizing circuit and the second synchronizing circuit based on a preset value; and a delay selecting circuit for selecting and outputting an output value of one of the first synchronizing circuit and the second synchronizing circuit based on one of the determination signal and the path setting signal.
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NEC Electronics Corporation
Phan Trong
Young & Thompson
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