Interface between buses attached with cached modules providing a

Details Interface between buses attached with cached modules providing a Interface between buses attached with cached modules providing a

1989-04-07

1991-12-10

Lee, Thomas C.

Boots, shoes, and leggings

36424341, 3642557, 3642402, 3649555, 36496432, 364964342, 364DIG1, 364DIG2, G06F 1208, G06F 1210, G06F 1316

Patent

active

050723693

ABSTRACT:
An interface circuit permits a first bus master connected to a first bus to directly access a main memory connected to a second bus while maintaining coherency between corresponding data in the main memory and a cache memory used by a second bus master on the second bus. The interface circuit maps selected first bus addresses to corresponding second bus addresses such that when a bus master on the first bus attempts to read or write access one of the mapped first bus addresses, the bus interface circuit responds by read or write accessing a corresponding address in the memory on the second bus. The bus interface circuit stores SNOOP data indicating which memory addresses contain data cached in the cache memory, and when accessing a cached memory address, the bus interface circuit places a signal on the second bus telling the second bus master to copy data from the cache memory into the main memory before the interface circuit performs a main memory read access or to copy data from the main memory to the cache memory after the interface circuit completes a main memory write access, thereby to maintain coherency between the main memory and the cache memory.

REFERENCES:
patent: 4025365 (1991-06-01), Mathur et al.
patent: 4747043 (1988-05-01), Rodman
patent: 4754394 (1988-06-01), Brantley, Jr. et al.
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 4785395 (1988-11-01), Keeley
patent: 5008813 (1991-04-01), Crane et al.
patent: 5029070 (1991-07-01), McCarthy et al.

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