Interface between a microprocessor and a coprocessor

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G06F 1516

Patent

active

045478490

ABSTRACT:
A nonclock-synchronous interface between a microprocessor and a coprocessor. A request line (404) from the coprocessor and an acknowledgment line (402) from the microprocessor provide for operand transfer from the coprocessor to the microprocessor. A busy line (410) and an error line (408) from the coprocessor allow the microprocessor to monitor the condition of the coprocessor. Data (406) are transferred through a data channel in the microprocessor using the full memory management and protection mechanism of the microprocessor so that the protection mechanism is not circumvented. A memory-read cycle is generated using the address taken from the memory-address register (401). The data is buffered inside the microprocessor and the coprocessor's request is acknowledged. The memory-address register is then incremented by a predetermined amount and an I/O write cycle is generated using a prewired address into the coprocessor. Data are transferred in the opposite direction in a similar manner using the prewired address to obtain the read data from the coprocessor which data is buffered inside of the microprocessor. A memory-write cycle is then generated by the processor using an address taken from the channel memory-address register and the data equal to the data buffered.

REFERENCES:
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patent: 4006466 (1977-02-01), Patterson et al.
patent: 4099236 (1978-07-01), Goodman et al.
patent: 4106092 (1978-08-01), Millers, III
patent: 4181936 (1980-01-01), Kober
patent: 4214305 (1980-07-01), Tokita et al.
patent: 4365294 (1982-12-01), Stokken

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