Interface arrangement for buffering communication information be

Details Interface arrangement for buffering communication information be Interface arrangement for buffering communication information be

1983-06-22

1985-06-25

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

H04Q 1104

Patent

active

045258317

ABSTRACT:
An interface arrangement is shown compensating for timing delays during transmission of communication information between a transmitting and receiving stage of a T-S-T digital switching system. The arrangement includes a buffer at the receiving stage having first and second storage files. During a first time slot communication information is written in the first file using control signals transmitted along with the communication information while simultaneously the second file is read using a local control signal. In the subsequent time slot the second file is written to and the first file is read, providing a one time slot slip between the transmitting and receiving stages.

REFERENCES:
patent: 3700819 (1972-10-01), Marcus
patent: 4081610 (1978-03-01), Valastro et al.
patent: 4206322 (1980-06-01), Lurtz
patent: 4320501 (1982-03-01), Le Dieu et al.
patent: 4392224 (1983-07-01), Mori et al.

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