Multiplex communications – Low speed asynchronous data system – Transmitting time of transition and logic state
Reexamination Certificate
2003-03-06
2004-09-14
Tan, Vibol (Department: 2819)
Multiplex communications
Low speed asynchronous data system
Transmitting time of transition and logic state
C370S470000, C370S503000, C710S104000, C365S201000, C326S093000, C326S086000, C713S400000
Reexamination Certificate
active
06791953
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interface apparatus and, more particularly, to an interface apparatus for transferring data between devices which are asynchronously operated.
2. Description of the Related Art
Conventionally, systems in which a CPU is connected to asynchronously-operated peripheral devices via a bus is well known. In the systems, a waiting cycle for a waiting operation until a synchronous timing with an operating clock (hereinbelow, referred to as an external clock) is inserted in a bus cycle of the CPU, thereby performing a control operation. It is requested that the performance due to the insertion of the waiting cycle is improved.
In order to respond to the above-mentioned request, as one related art, Japanese Unexamined Patent Application Publication No. 8-335162 discloses an “input interface circuit”. In the input interface circuit, data from a peripheral device is fetched and held both at a rising edge and at a falling edge of an external clock CLK. A reading signal RS for instructing an operation to fetch the data from the peripheral device is outputted from a CPU and then the input interface circuit samples the external clock CLK by the reading signal RS from the CPU. If data as a result of sampling is at the high level (hereinafter, referred to as an H level), the data fetched and held at the rising edge is selected and is sent to the CPU. If the data as the result of sampling is at the low level (hereinafter, referred to as an L level), the data fetched and held at the falling edge is selected and is sent to the CPU.
Further, as another related art, Japanese Unexamined Patent Application Publication No. 2000-76180 discloses a bus connecting apparatus and an information processing system in which the transfer performance is improved by effectively using a buffer. Furthermore, Japanese Unexamined Patent Application Publication No. 6-274460 discloses a data communication apparatus between processors running at different speeds in which the operating efficiency of a fast processor is improved.
In addition, Japanese Unexamined Patent Application Publication No. 11-338821 discloses an asynchronous data transfer apparatus in which the overhead upon transferring data to a low-speed bus to a high-speed bus is reduced as much as possible with only a single-stage data buffer necessary for synchronization with the clock and the system performance is improved by continuously using data at the low-speed bus.
However, in the input interface circuit disclosed in Japanese Unexamined Patent Application Publication No. 8-335162, if a pulse width of the reading signal RS is 50% or more of that of the external clock CLK, dangerously, normal data is not obtained because the data from the peripheral device changes even during the reading operation of the CPU.
Further, the level of the external clock CLK is used to select any of the data fetched at the rising edge of the external clock CLK and the data fetched at the falling edge. Therefore, the design and adjustment are troublesome because they are strictly performed to always set a duty ratio of the external clock CLK constant.
SUMMARY OF THE INVENTION
The present invention is devised in consideration of the above-mentioned situation. Accordingly, it is an object of the present invention to provide an interface apparatus in which data is normally transferred between a plurality of devices which are asynchronously operated irrespective of periods of operating clocks of the devices.
In order to accomplish the foregoing object, according to a first aspect of the present invention, there is provided an interface apparatus comprising: a pulse generating unit which detects the change of reading target data and generates a start pulse; an adjusting unit which generates an adjusting signal that changes from a first signal level to a second signal level in response to the start pulse generated by the pulse generating unit; a register unit comprising a data holding register which fetches first reading target data synchronously with a clock that is externally supplied when the adjusting signal is at the second signal level, and holds the data and outputs the data as second reading target data when the adjusting signal is at the first signal level; and a driver unit which outputs the first reading target data synchronously with a reading signal that is asynchronous with the clock when the adjusting signal is at the second signal level, and outputs the second reading target data synchronously with the reading signal when the adjusting signal is at the first signal level.
Further, according to a second aspect of the present invention, there is provided an interface apparatus set between a peripheral device and a bus, comprising: an adjusting unit which generates an adjusting signal that changes from a first signal level to a second signal level in response to a start pulse inputted from the peripheral device; a register unit comprising a data holding register which fetches first reading target data synchronously with a clock that is supplied from the peripheral device when the adjusting signal is at the second signal level, and holds and outputs the data as second reading target data when the adjusting signal is at the first signal level; and a driver unit which outputs the first reading target data synchronously with a reading signal that is externally supplied asynchronously with the clock when the adjusting signal is at the second signal level, and outputs the second reading target data synchronously with the reading signal when the adjusting signal is at the first signal level.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.
REFERENCES:
patent: 4353128 (1982-10-01), Cummiskey
patent: 5919254 (1999-07-01), Pawlowski et al.
patent: 6052386 (2000-04-01), Achilleoudis et al.
patent: 6108352 (2000-08-01), Sferrazza et al.
patent: 6330200 (2001-12-01), Ooishi
patent: 6-274460 (1994-09-01), None
patent: 8-335162 (1996-12-01), None
patent: 11-338821 (1999-12-01), None
patent: 2000-076180 (2000-03-01), None
Hashimoto Tetsuya
Ogawa Makoto
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
Tan Vibol
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