Interface and control circuit for regulating data flow in a SCSI

Details Interface and control circuit for regulating data flow in a SCSI Interface and control circuit for regulating data flow in a SCSI

1993-03-11

1996-08-06

Lim, Krisna

Boots, shoes, and leggings

395872, 395309, 364DIG1, G06F 1338

Patent

active

055443265

ABSTRACT:
A single chip SCSI controller circuit has a pair of input and output first in, first out (FIFO) buffers as well as a main buffer. The circuit supports synchronous and asynchronous data transfers which are fully compatible with the SCSI-II specification. A mode select pin may be selectively actuated by the user or by attached interface circuitry to configure the chip for either microchannel architecture (MCA) or industry standard architecture (ISA) compatibility.

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National Semiconductor, Advanced Peripherals Mass Storage Handbook, Section 6, SCSI Bus Interface Circuits, pp. 6-3-6-22.

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