Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-04-07
2004-11-23
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S306000, C257S307000, C257S311000, C257S534000
Reexamination Certificate
active
06822312
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to capacitor structures in metal-oxide-semiconductors (MOS), and in particular, to an interdigitated multilayer (IM) capacitor structure for deep sub-micron complementary MOS (CMOS), which is formed by interconnecting conductive lines in multiple levels through vias to construct a parallel array of vertical capacitor plates, and interconnecting the plates to the opposing nodes in an alternating manner so that the plates have alternating electrical polarities.
BACKGROUND OF THE INVENTION
Conventional capacitor structures for deep sub-micron CMOS are typically constructed with two flat parallel plates separated by a thin dielectric layer. The plates are formed by layers of conductive material, such as metal or polysilicon. The capacitor structure is usually isolated from the substrate by an underlying dielectric layer. To achieve high capacitance density in these devices, additional plates are provided.
FIGS. 1A and 1B
illustrate a representative conventional multi-parallel plate capacitor
10
in a deep sub-micron CMOS structure. The capacitor structure
10
includes a vertical stack of electrically conductive lines
12
separated by dielectric layers
13
. The conductive lines
12
and dielectric layers
13
are constructed over a semiconductor substrate
11
. The conductive lines
12
form the plates or electrodes of the capacitor
10
. The plates
12
are electrically connected together in an alternating manner such that all the “A” plates are of a first polarity and all the “B” plates are of a second polarity, opposite to the first polarity.
A major limitation associated with parallel plate capacitor structures is that the minimum distance between the plates does not change as geometries in CMOS processes are scaled down. Hence, gains in capacitance density are not realized during such down scaling.
Various other capacitor structures with high capacitance densities, such as double polysilicon capacitors and gate-oxide capacitors, are known in the art. Double polysilicon capacitors, however, do not lend themselves to deep sub-micron CMOS processes. Gate-oxide capacitors are generally not used in deep sub-micron CMOS processes because they have large gate areas which cause yield and reliability issues, they generate capacitances which vary with voltage, and may experience high voltages that can breakdown the gate-oxide.
Trench capacitor structures for dynamic random access memories (DRAMs) have high capacitance densities. Such capacitors are formed by etching a trench in the substrate and filling the trench with conductive and dielectric material to form a vertical capacitance structure. However, trench capacitors are costly to fabricated because they add etching and trench filling processes.
Interdigitated capacitor structures are used in microwave applications. These capacitors have closely placed, interdigitated conductive line structures which produce fringing and cross-over capacitances therebetween to achieve capacitance. However, the cross-over capacitance produced by interdigitated capacitors is limited to a single conductor level.
Accordingly, a need exists for an improved capacitor structure for deep sub-micron CMOS, which takes advantage of shrinking semiconductor process geometries and can be manufactured inexpensively.
SUMMARY OF THE INVENTION
A capacitor structure comprising a first level of electrically conductive parallel lines and at least a second level of electrically conductive parallel lines disposed over the lines in the first level, the lines of the first and second levels being arranged in vertical rows. A dielectric layer is disposed between the first and second levels of conductive lines. One or more vias connect the first and second level lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. Electrically opposing nodes form the terminals of the capacitor. The parallel array of vertical capacitor plates are electrically connected to the nodes in an alternating manner so that the plates have alternating electrical polarities.
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patent: 5939766 (1999-08-01), Stolmeijer et al.
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Patent Abstracts of Japan, vol. 1996, No. 02, Feb. 29, 1996, JP 07283076 A.
Sowlati Tirdad
Vathulya Vickram
Koninklijke Philips Electronics , N.V.
Nadav Ori
Zawilski Peter
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