Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
2001-10-04
2002-12-17
Dinkins, Anthony (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
Reexamination Certificate
active
06496355
ABSTRACT:
BACKGROUND OF THE INVENTION
The present subject matter generally concerns a multilayer decoupling capacitor characterized by low inductance, and more particularly concerns such a multilayer capacitor with interdigitated electrode layer portions as well as ball grid array (BGA) terminations.
Integrated circuits (ICs) have been implemented for some time, but many specific features of these ICs affect the design criteria for electronic components and corresponding procedures for mounting such components. With increased functionality of integrated circuit components, the design of electronic components must become increasingly more efficient. The miniaturization of electronic components is a continuing trend in the electronics industry, and it is of particular importance to design parts that are sufficiently small, yet simultaneously characterized by high operating quality. Components are desired that are small in size and that have reliable performance characteristics, yet can also be manufactured at relatively low costs.
Component miniaturization enables higher density mounting on circuit boards or other foundations. Thus the spacing between components is also a limiting factor in present integrated circuit designs. Since spacing is such a critical design characteristic, the size and location of termination means or elements for IC components is also a significant design characteristic.
One specific electronic component that has been used in IC applications is the decoupling capacitor. Decoupling capacitors are often used to manage electrical noise problems that occur in circuit applications. They provide stable, local charge sources required to switch and refresh the logic gates used in present digital circuits. A dramatic increase in the speed and packing density of integrated circuits requires advancements in decoupling capacitor technology. When high-capacitance decoupling capacitors are subjected to the high frequencies of many present applications, performance characteristics become increasingly more important. One way to achieve improved performance is by lowering the inductance of the device. Thus, it is ideal that such capacitive structures provide low equivalent series inductance (ESL) in order to maintain circuit efficiency.
Several design aspects have been implemented that reduce the self and mutual inductance of decoupling capacitors. Reducing the current path will lower self inductance. Since the current often has to travel the entire length of the capacitor, termination on the longer ends of the structure will reduce the current path. If the current in adjacent capacitor electrodes flows in opposite directions it will reduce the mutual inductance in a capacitor. Multiple terminations as utilized in interdigitated capacitor technology lowers the inductance value.
Another approach to lowering the ESL of a decoupling capacitor is to minimize interconnect induction that results from termination configurations and mounting systems. Typical termination schemes incorporate long traces to the capacitor electrode pads. Such a connection is characterized by high inductance and often prohibits very close spacing between components. Thus, a more efficient termination is desired that has low ESL and that facilitates high component density for integrated circuits. It is also ideal to provide such an efficient termination scheme without decreasing the volumetric efficiency of the component.
Yet another contribution to lowering the ESL of a decoupling capacitor lies in reducing the current path between a ground plane or power plane in an integrated circuit to the electrode plates in a multilayer capacitor configuration. Typical multilayer capacitor designs require relatively thick cover layers on both top and bottom of such a multilayer configuration. These protective layers ideally provide sufficient bulk to withstand the stress of typical glass/metal frit that must be fired to a capacitor body. This typical need for protective outer layers hinders potential reduction of loop inductance.
In the context of decoupling capacitors, it is often ideal to incorporate other design characteristics based on specific applications. Customers of capacitor manufacturers often specify such choices, including capacitor packaging configuration and termination composition. In particular, it is convenient to have capacitors that can encompass either land grid array or area grid array designs. It will be appreciated throughout the remainder of this disclosure that a land grid array design corresponds to attachments located on the periphery of given surface of a component package; alternatively, an area grid array design corresponds to attachments distributed to form a matrix-type configuration over an entire given surface (periphery and internal regions thereof), of a component package. It is ideal to incorporate such options into a capacitor design in a cost-effective and convenient manner.
While examples of various aspects and alternative embodiments are known in the field of multilayer decoupling capacitors, no one design is known that generally encompasses all of the above-referenced preferred capacitor characteristics.
U.S. Pat. No. 6,064,108 shows an example of a multilayer capacitor that incorporates an arrangement of “interdigitated” capacitor plates. Such '108 patent represents an exemplary electrode configuration that enables reliable high-capacitance multilayer devices.
U.S. Pat. No. 5,661,450 discloses resistor arrays with low inductance termination schemes. Such arrays include conductive vias through a substrate with attached solder balls. This configuration is exemplary of a design that achieves low inductance connections for an integrated circuit environment.
U.S. Pat. Nos. 5,666,272 and 5,892,245 disclose examples of ball grid array (BGA) packages that facilitate increased component density on circuit boards.
U.S. Pat. No. 6,097,609 shows an exemplary packaging assembly that is compatible with both ball grid array (EGA) and land grid array (LGA) design configurations.
U.S. Pat. No. 5,880,925 discloses an exemplary multilayer capacitor with an interdigitated arrangement of lead structures.
Japanese Patent Nos. 7-37756, and 737795 reference capacitor arrays capable of high density component packaging.
Additional patents provide varied examples of capacitor designs, as follows.
U.S.
ISSUE
PAT. NO.:
INVENTOR:
DATE
TITLE:
6,114,756
Kinsman
09/05/2000
INTERDIGITATED
CAPACITOR DESIGN FOR
INTEGRATED
CIRCUIT LEADFRAMES
5,973,391
Bischoff et
10/26/1999
INTERPOSER WITH
al.
EMBEDDED CIRCUITRY
AND METHOD FOR
USING THE SAME TO
PACKAGE
MICROELECTRONIC
UNITS
5,905,633
Shim et al.
05/18/1999
BALL GRID ARRAY
SEMICONDUCTOR
PACKAGE USING A
METAL CARRIER RING
AS A HEAT SPREADER
5,893,724
Chakravorty
04/13/1999
METHOD FOR FORMING A
et al.
HIGHLY RELIABLE AND
PLANAR BALL GRID
ARRAY PACKAGE
5,892,290
Chakravorty
04/06/1999
HIGHLY RELIABLE AND
et al.
PLANAR BALL GRID
ARRAY PACKAGE
5,880,921
Tham et al.
03/09/1999
MONOLITHICALLY
INTEGRATED SWITCHED
CAPACITOR BANK
USING MICRO ELECTRO
MECHANICAL SYSTEM
(MEMS) TECHNOLOGY
5,872,399
Lee
02/16/1999
SOLDER BALL LAND
METAL STRUCTURE OF
BALL GRID
SEMICONDUCTOR
PACKAGE
5,864,470
Shim et al.
01/26/1999
FLEXIBLE CIRCUIT
BOARD FOR BALL
GRID ARRAY
SEMICONDUCTOR
PACKAGE
5,855,323
Yost et al.
01/05/1999
METHOD AND
APPARATUS FOR
JETTING,
MANUFACTURING AND
ATTACHING UNIFORM
SOLDER BALLS
5,821,827
Mohwinkel
10/13/1998
COPLANAR OSCILLATOR
et al.
CIRCUIT STRUCTURES
5,787,580
Woo
08/04/1998
METHOD FOR MAKING
RADIO-FREQUENCY
MODULE BY BALL
GRID ARRAY PACKAGE
5,724,728
Bond et al.
03/10/1998
METHOD OF MOUNTING
AN INTEGRATED CIRCUIT
TO A MOUNTING
SURFACE
5,717,245
Pedder
02/10/1998
BALL GRID ARRAY
ARRANGEMENT
5,642,265
Bond et al.
06/24/1997
BALL GRID ARRAY
PACKAGE WITH
DETACHABLE MODULE
5,641,113
Somaki et al.
06/24/1997
METHOD FOR
FABRICATING AN
ELECTRONIC DEVICE
HAVING SOLDER JOINTS
5,637,832
Danner
06/10/1997
SOLDER BALL ARRAY
AND METHOD OF
PREPARATION
5,594,275
Kwon et al.
01/14/1997
J-LEADED
SEMICONDUCTOR
PACKAGE HAVING A
PLURALITY OF STACKED
BALL GRID ARRAY
PACKAGES
5,5
Brown Thomas
Galvagni John L.
Ritter Andrew P.
AVX Corporation
Dinkins Anthony
Dority & Manning
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