Interconnects for semiconductor light emitting devices

Details Interconnects for semiconductor light emitting devices Interconnects for semiconductor light emitting devices

2005-09-13

2008-03-25

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C257SE21499

Reexamination Certificate

active

07348212

ABSTRACT:
A semiconductor light emitting device including a light emitting layer disposed between an n-type region and a p-type region and contacts electrically connected to the n-type region and the p-type region is connected to a mount. A metal layer arbitrarily patterned to cover at least 20% of the area of the semiconductor light emitting device is plated on either a metal layer formed on the mount or a metal layer formed on one of the contacts. The plated metal layer may replace other known interconnecting techniques such as stud bumps. The semiconductor light emitting device is physically connected to the mount by causing interdiffusion between the contact surfaces of the metal layers. In some embodiments, a layer of solder is formed over the plated metal layer, and then the semiconductor light emitting device is physically connected to the mount by heating the solder.

REFERENCES:
patent: 5777433 (1998-07-01), Lester et al.
patent: 6274924 (2001-08-01), Carey et al.
patent: 6486499 (2002-11-01), Krames et al.
patent: 2005/0045901 (2005-03-01), Wall, Jr.
patent: 2005/0072835 (2005-04-01), Choi et al.
patent: 2005/0184387 (2005-08-01), Collins, III et al.
patent: 2006/0138444 (2006-06-01), Chio et al.

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