Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-12-11
2003-08-12
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S537000, C324S765010
Reexamination Certificate
active
06605951
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to testing semiconductor devices formed on a wafer. More particularly, the present invention relates to a new and improved method and apparatus for placing power and signal probes on a semiconductor die cut from the wafer and applying power and signals to the die while performing testing and failure analysis.
BACKGROUND OF THE INVENTION
Failure analysis of a semiconductor device is done with a variety of techniques used to locate, analyze, and identify faults in the device. The semiconductor integrated circuit (IC) or chip is typically formed on a silicon substrate using a layering technique which results in a multilayered device composed of various layers of metal, polysilicon, dielectric and other materials. Many ICs are fabricated at once on a wafer. Thereafter, using one type of testing and failure analysis technique, the wafer is cut into die with each die or chip containing an IC. Testing or failure analysis is then performed on the die. If the IC is meets the functional specifications, the die is placed into a package and leads are attached between bond pads of the IC and bond pads of the package.
Typical failure analysis techniques used on the front side of the die include mechanical probing, electron beam probing, photo emission microscopy, and optical beam induced current (“OBIC”). The die is placed on the platen of a testing station and power and signal probes are placed on the front surface of the die to power up the IC. The failure analysis techniques are then used on the front surface of the die to detect and isolate faults in the IC. Some optical failure analysis techniques, such as emission microscopy and OBIC, are also performed on the back side of the die.
Photo emission microscopy is a “hot spot” detection technique which detects photons emitted from faults in the IC. The type of faults which typically generate a photo emission include junction defects, contact spiking, hot electrons, latch-up, poly filaments, and substrate damage and contamination. The photo emissions are typically the result of electron-hole recombinations which generate light primarily in the infrared region of the light spectrum. The photo emissions are transmitted through semi-transparent dielectric layers, polysilicon layers, and passivity layers, and emerge from the front side of the die where they may be seen by viewing the front side of the die. The photo emissions are also transmitted through the substrate of the die and emerge from the back side of the die where they may be seen by viewing the back surface of the die.
In photo emission microscopy, an infrared optical microscopic device or other infrared optical viewing device, such as a charge coupled device (CCD) camera with a monitor, is used to obtain an image of the photo emissions from the back side of the die. The photo emission image is overlaid on a bright field reference image of the IC to isolate and identify the fault sites associated with the photo emissions. Power and signals must be supplied to the IC in the photo emission microscopy technique. The power and signals are supplied to the IC by placing power and signal probes on the die and supplying power and signals from external sources to the probes when performing the testing or failure analysis.
The effectiveness of optical failure analysis techniques used on the front side of the die is diminished because of the increased complexity of many ICs. In particular, ICs are being manufactured with additional metal interconnect layers. The increasing number of layers makes photo emission microscopy from the front side of the die difficult, if not impossible, because of the lack of visibility of the photo emissions from the front side of the die. The additional metal interconnect layers include as many as six upper layers for power busses, high density signal routing signal lines, and bond pads. The metal interconnect layers are place above the substrate of the wafer where active devices, such as transistors, are formed. Active transistors are generally the source of most faults detectable using optical failure analysis techniques on the front side of the die. The photons emitted from the fault cannot pass through the numerous opaque metal interconnect layers of the device. Instead, the photon emissions pass between or are scattered around the metal interconnect layers, preventing the detection of photo emissions from the surface of the die or otherwise decreasing the accuracy of locating the fault. The effectiveness of the optical failure analysis techniques used on the front side of the die is diminished because the additional metal interconnect layers obstruct the visibility of faults in the active devices. However, optical photo emission microscopy can be effectively used on the back side of the die where it is less likely that faults are obstructed by metal interconnect layers.
If the IC on the die is found to be functional, the die is placed into the package for further testing. Typically, wire bonding is then used to directly connect bond pads of the die to bond pads of the package. Alternatively, tape-automated bonding is used to connect the bond pads of the die to bond pads of a tape bond which form the bond pads of the package. The bond pads of the tape bond are connected to pins of the package with leads to complete an electrical connection between the bond pads of the die and the pins of the package. The packaged IC is then tested for functionality and electrical specifications.
In tape-automated bonding, interconnections to connect the IC to the bond pads of the tape bond are patterned on a polymer tape. The interconnections are typically metal tracks or conductors on the tape to contact bond pads on the periphery of the die. The tape bond is attached to the bare die by contacting the bond pads to the metal tracks or the metal bumps. An adhesive is used to secure the tape bond to the die.
Application of the testing and failure analysis techniques on the back side of the die is complicated with existing die probing techniques. Typically, the die is affixed to a transparent support beneath an emission microscope or an infrared sensitive CCD camera. Power and signal probes are then placed on the contact pads of the semiconductor device after the die is inverted. The process of contacting the probes to the semiconductor device typically involves viewing the surface of the inverted die on a video monitor while mechanically manipulating the probes to place probes tips on the contact pads of the IC on the die. This process is complicated in terms of eye-to-hand coordination since the video image is a reverse image of the die from the viewpoint of a normal viewing. Also, the equipment operator must view the die surface indirectly though the video monitor rather than viewing the die surface directly while placing the probes on the die. The process of connecting the probes to the semiconductor device is tedious, time-consuming and prone to error.
Application of the testing and failure analysis techniques on the front side of the die is also complicated with existing probing techniques. The probes are typically placed on the front side of the die by contacting tips of the probes to the very small contact pads on the front side of the die by using a microscope. The probes have a relatively long, cantilevered-like arm which extend from micrometer-like devices used to adjust the mechanical position of the tips of the probes. Because of the relatively long arm of the probes and their cantilevered extension from the adjustment mechanism, the movement of the tip of the probes is magnified, which makes it difficult, tedious and time-consuming to precisely and accurately position the probe tip on the desired contact pad of the IC. Moreover, the probe tip is also subject to natural environmental vibrations because of the magnification effect of the relatively long arm of the probe. Consequently, connecting the probes to the semiconductor device for front side failure analysis techniques is also difficult and prone to error.
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Cuneo Kamand
Hollington Jermele
John R. Ley, LLC
LSI Logic Corporation
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